#### NextREG 83 (53h) – MMU Slot 3 Control

Group Name	R	W	Data Bits								Description	H	D
			7	6	5	4	3	2	1	0
MMU Slot 3 Control	■	■	•	•	•	•	•	•	•	•	8K RAM page for address 6000h–7FFFh		*

\* Default **11** (**0Bh**) – Pages range from **0** to **223** on a fully expanded Next #### NextREG 84 (54h) – MMU Slot 4 Control

Group Name	R	W	Data Bits								Description	H	D
			7	6	5	4	3	2	1	0
MMU Slot 4 Control	■	■	•	•	•	•	•	•	•	•	8K RAM page for address 8000h–9FFFh		*

\* Default **4** (**04h**) – Pages range from **0** to **223** on a fully expanded Next #### NextREG 85 (55h) – MMU Slot 5 Control

Group Name	R	W	Data Bits								Description	H	D
			7	6	5	4	3	2	1	0
MMU Slot 5 Control	■	■	•	•	•	•	•	•	•	•	8K RAM page for address A000h–BFFFh		*

\* Default **5** (**05h**) – Pages range from **0** to **223** on a fully expanded Next #### NextREG 86 (56h) – MMU Slot 6 Control

Group Name	R	W	Data Bits								Description	H	D
			7	6	5	4	3	2	1	0
MMU Slot 6 Control	■	■	•	•	•	•	•	•	•	•	8K RAM page for address C000h–DFFFh		*

\* Default **0** (**00h**) – Pages range from **0** to **223** on a fully expanded Next #### NextREG 87 (57h) – MMU Slot 7 Control

Group Name	R	W	Data Bits								Description	H	D
			7	6	5	4	3	2	1	0
MMU Slot 7 Control	■	■	•	•	•	•	•	•	•	•	8K RAM page for address E000h–FFFFh		*

\* Default **1** (**01h**) – Pages range from **0** to **223** on a fully expanded Next #### NextREG 96 (60h) – Copper Data 8-bit Write

Group Name	R	W	Data Bits								Description	H	D
			7	6	5	4	3	2	1	0
Copper Instruction 8-bit		■	•	•	•	•	•	•	•	•	Byte to write to copper instruction memory

Each Copper Instruction is two-bytes long. After a write, the Copper address is auto-incremented to the next memory position #### NextREG 97 (61h) – Copper Address LSB

Group Name	R	W	Data Bits								Description	H	D
			7	6	5	4	3	2	1	0
Copper memory address LSB	■	■	•	•	•	•	•	•	•	•	Copper instruction memory address (LSB)		0

Copper memory addresses range over 0 through 2047 (7FFh) #### NextREG 98 (62h) – Copper Control

Group Name	R	W	Data Bits								Description	H	D
			7	6	5	4	3	2	1	0
Copper Memory Address MSB	■	■	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	•	•	•	Copper Instruction Memory Address (MSB)		0
Copper Start Control	■	■	0	0	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	Copper fully stopped		*
			0	1	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	Copper start, exec from 0, loop
			1	0	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	Copper start, exec from last, loop
			1	1	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	Copper start, exec from 0, rest. at raster 0,0

\* Soft reset defaults to **000**\ Copper memory addresses range from **0** through **2047** (**7FFh**)\ Note: Writing the same copper start control value does not reset the copper #### NextREG 99 (63h) – Copper Data 16-bit Write

Group Name	R	W	Data Bits								Description	H	D
			7	6	5	4	3	2	1	0
Copper data		■	•	•	•	•	•	•	•	•	1st write MSB, 2nd write LSB		0

The 16-bit value is written in pairs. The first 8-bits are the MSB and are destined for an even copper instruction address. The second 8-bits are the LSB and are destined for an odd copper instruction address\ After each write, the copper address is auto-incremented to the next memory position.\ After a write to an odd address, the entire 16-bits is written to copper memory at once #### NextREG 100 (64h) – Vertical Line Count Offset

Group Name	R	W	Data Bits								Description	H	D
			7	6	5	4	3	2	1	0
Line counter offset	■	■	•	•	•	•	•	•	•	•	Offset added to the vertical line counter*

\* Affects Copper, line interrupt and active line count\ Normally the ULA's pixel row **0**, aligns with vertical line count **0**. With a non-zero offset, the ULA's pixel row **0** will align with the vertical line offset. For example if the offset is **32** then vertical line **32** will correspond to the first pixel row in the ULA and vertical line **0** will align with the first pixel row of *Layer 3* (Tilemap) and the *Sprite Layer*\ **NOTE:** Since a change in offset takes effect when the ULA reaches row **0**, the change can take up to one frame to occur #### NextREG 104 (68h) – ULA Control

Group Name	R	W	Data Bits								Description	H	D
			7	6	5	4	3	2	1	0
Stencil Mode control	■	■	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: dark green]	•	Enable Stencil Mode¹		0
Reserved	■		[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: dark green] 0	[colour: pink]	Reserved, must be 0		0
ULA Half-Pixel Scroll	■	■	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	•	[colour: dark green]	[colour: pink]	ULA Half-Pixel Scroll enabled²		0
ULAplus Control	■	■	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	•	[colour: pink]	[colour: dark green]	[colour: pink]	ULAplus Enabled		0
Extended keys in 8x5 matrix	■	■	[colour: pink]	[colour: pink]	[colour: pink]	•	[colour: pink]	[colour: pink]	[colour: dark green]	[colour: pink]	Cancel entries in matrix for extended keys		0
Blend Colour Used in SLU modes 6 & 7	■	■	[colour: pink]	0	0	[colour: pink]	[colour: pink]	[colour: pink]	[colour: dark green]	[colour: pink]	ULA Colour		0
			[colour: pink]	1	0	[colour: pink]	[colour: pink]	[colour: pink]	[colour: dark green]	[colour: pink]	ULA + Tilemap mix
			[colour: pink]	1	1	[colour: pink]	[colour: pink]	[colour: pink]	[colour: dark green]	[colour: pink]	Tllemap Colour
			[colour: pink]	0	1	[colour: pink]	[colour: pink]	[colour: pink]	[colour: dark green]	[colour: pink]	No Colour Blending
Output Control	■	■	•	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: dark green]	[colour: pink]	Disable ULA output		0

1 When both the ULA and Layer 3 (Tilemap) are enabled, if either are transparent, the result is transparent otherwise the result is a logical AND of both colours\ 2 Setting may change #### NextREG 105 (69h) – Display Control 1

Group Name	R	W	Data Bits								Description	H	D
			7	6	5	4	3	2	1	0
Port 255 (FFh) “Timex” alias	■	■	[colour: pink]	[colour: pink]	•	•	•	•	•	•	Port 255 (FFh) alias
Port 32765 (7FFDh):D3 alias	■	■	[colour: pink]	•	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	ULA Shadow Display Enable
Port 4667 (123Bh):D1 alias	■	■	•	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	Layer 2 Enable

#### NextREG 106 (6Ah) – Layer 1,0 (LoRes) Control

Group Name	R	W	Data Bits								Description	H	D
			7	6	5	4	3	2	1	0
LoRes | ULAplus palette Offset	■	■	[colour: dark green]	[colour: dark green]	[colour: pink]	[colour: pink]	•	•	•	•	LoRes Palette Offset		0
			[colour: dark green]	[colour: dark green]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	•	•	ULAplus Palette Offset		0
Radastan Mode DFILE Source	■	■	[colour: dark green]	[colour: dark green]	[colour: pink]	•	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	Timex DFILE source¹		0
LoRes mode	■	■	[colour: dark green]	[colour: dark green]	•	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	Radastan Mode Enable		0
Reserved	■	■	[colour: dark green] 0	[colour: dark green] 0	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	Reserved, must be 0

1 Layer 1,0 (LoRes) occupies both Timex display files but Radastan mode has only half the colour depth thus occupies only one DFILE – at either **16384** (**4000h**) or **24576** (**6000h**). When this bit is set, the source DFILE used is the opposite of the ULA so that Radastan can co-exist with the normal Layer 0 (ULA) screen #### NextREG 107 (6Bh) – Layer 3 (Tilemap) Control

Group Name	R	W	Data Bits								Description	H	D
			7	6	5	4	3	2	1	0
Layer 3 Priority	■	■	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: dark green]	[colour: pink]	•	Tilemap on top of ULA Enable		0
512 Tile mode Control	■	■	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: dark green]	•	[colour: pink]	Activate 512 Tile mode¹		0
Reserved	■	■	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: dark green] 0	[colour: pink]	[colour: pink]	Reserved, must be 0		0
Text mode Control	■	■	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	•	[colour: dark green]	[colour: pink]	[colour: pink]	Text mode Enable		0
Layer 3 palette Select	■	■	[colour: pink]	[colour: pink]	[colour: pink]	0	[colour: pink]	[colour: dark green]	[colour: pink]	[colour: pink]	Palette 0		0
			[colour: pink]	[colour: pink]	[colour: pink]	1	[colour: pink]	[colour: dark green]	[colour: pink]	[colour: pink]	Palette 1
Attribute Entry Control	■	■	[colour: pink]	[colour: pink]	•	[colour: pink]	[colour: pink]	[colour: dark green]	[colour: pink]	[colour: pink]	Attribute entry Disable²		0
Layer 3 Size Control	■	■	[colour: pink]	0	[colour: pink]	[colour: pink]	[colour: pink]	[colour: dark green]	[colour: pink]	[colour: pink]	40 x 32		0
			[colour: pink]	1	[colour: pink]	[colour: pink]	[colour: pink]	[colour: dark green]	[colour: pink]	[colour: pink]	80 x 32
Layer 3 Control	■	■	•	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: dark green]	[colour: pink]	[colour: pink]	Tilemap Enable		0

1 If this bit is set, **NextREG 108 (6Ch):D0** changes meaning\ 2 If this bit is set then the Layer 3 tilemap entries are only a single byte **Tile ID** and the attribute byte comes from **NextREG 108 (6Ch)** instead #### NextREG 108 (6Ch) – Default Layer 3 (Tilemap) Attribute*

Group Name	R	W	Data Bits								Description	H	D
			7	6	5	4	3	2	1	0
If 512 Tile mode is disabled	■	■	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	•	ULA over Layer 3		0
If 512 Tile mode is enabled	■	■	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	•	Bit 8 of the tile number
Rotate 90° Control	■	■	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	•	[colour: pink]	Rotate		0
Y Mirror Control	■	■	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	•	[colour: pink]	[colour: pink]	Y Mirror		0
X Mirror Control	■	■	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	•	[colour: pink]	[colour: pink]	[colour: pink]	X Mirror		0
Palette Offset	■	■	•	•	•	•	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	Palette Offset		0

\* Active if **NextREG 107 (6Bh):D5** is set. If **NextREG 107 (6Bh):D3** is set, the palette offset is extended to **D7:D1** replacing the rotate and mirror bits #### NextREG 110 (6Eh) – Layer 3 (Tilemap) Base Address

Group Name	R	W	Data Bits								Description	H	D
			7	6	5	4	3	2	1	0
MSB of Layer 3 base address in Banks 5 & 7	■	■	[colour: pink]	[colour: dark green] 0	•	•	•	•	•	•	Address in bank 5 or bank 7 – Entered		*
	■	■	•	[colour: dark green]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	together with bit 7 – bit 6 is 0

\* Soft Reset value is **108** (**6Ch**) read as **44** (**2Ch**)\ Writes are the MSB of an address in bank 5 **16384** - **32767** (**4000h** – **7FFFh**) or in bank 7 **49152** - **65535** (**C000h** – **FFFFh**) with **D6** ignored and always read back as 0. This means tile definitions start on 256-byte boundaries\ Bank 7 addresses wrap around its 8K boundary #### NextREG 111 (6Fh) – Layer 3 (Tilemap) - Tile Definitions Base Address

Group Name	R	W	Data Bits								Description	H	D
			7	6	5	4	3	2	1	0
MSB of Layer 3 Tile definitions base address in Banks 5 & 7	■	■	[colour: pink]	[colour: dark green] 0	•	•	•	•	•	•	Address in bank 5 or bank 7 – Entered		*
	■	■	•	[colour: dark green]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	together with bit 7 – bit 6 is 0

\* Soft Reset value is **76** (**4Ch**) read as **12** (**0Ch**)\ Writes are the MSB of an address in bank 5 **16384** - **32767** (**4000h** – **7FFFh**) or in bank 7 **49152** - **65535** (**C000h** – **FFFFh**) with **D6** ignored and always read back as 0. This means tile definitions start on 256-byte boundaries\ Bank 7 addresses wrap around its 8K boundary #### NextREG 112 (6Ah) – Layer 2 Resolution Control*

Group Name	R	W	Data Bits								Description	H	D
			7	6	5	4	3	2	1	0
Layer 2 Palette Offset	■	■	[colour: dark green]	[colour: dark green]	[colour: pink]	[colour: pink]	•	•	•	•	Layer 2 4-bit Palette Offset		0
Layer 2 Resolution Select**	■	■	[colour: dark green]	[colour: dark green]	0	0	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	256 x 192 x 8bpp (Layer 2 standard)		0
			[colour: dark green]	[colour: dark green]	0	1	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	320 x 256 x 8bpp (Layer 2, Mode 2)
			[colour: dark green]	[colour: dark green]	1	0	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	640 x 256 x 4bpp (Layer 2, Mode 3)
Reserved	■	■	[colour: dark green] 0	[colour: dark green] 0	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	Reserved, must be 0

\* The *Layer 2* screen occupies **48K** or **80K**, which is stored in **3** consecutive **16 KB** banks for **256 x 192 x 8bpp** or **5** consecutive banks for **320 x 256** and **640 x 256** resolutions. When in *NextZXOS/NextBASIC*, banks **9 - 11** are used for the visible and shadow *Layer 2(,0)* screen (after power-on, the hardware default to banks **8 - 10** for displayed and **11 - 13** for shadow screen but this gets modified by *NextZXOS* – See *Chapter 23*). These can be set using *Layer 2* RAM Page **NextREG 18 (12h)** and *Layer 2* RAM Shadow Page **NextREG 19 (13h)** (avoid banks **5**, **7** and **8** to be used as *Layer 2* screen, unless you are familiar with SRAM and BRAM of the board and how the ULA screen memory has special treatment in Next's FPGA) \*\* Each pixel of *Layer 2* is assigned 1 byte (8-bits) (in **8bpp** modes) or 1 nibble (4-bits) (in **640 x 256 x 4bpp** mode) of video memory. This means *Layer 2* consumes a total of either **48K** or **80K** of memory. The memory is divided in **16K** "*strips*" filling one standard Spectrum bank. In **256x192** mode the strips are horizontal so that **16K** represent **64** vertical lines on the display. In **320x256** and **640x256** modes the strips are vertical so that each **16K** corresponds to **64** or **128** columns respectively – See *Chapters 15* and *16* #### NextREG 113 (71h) – Layer 2 Horizontal Scroll Control MSB

Group Name	R	W	Data Bits								Description	H	D
			7	6	5	4	3	2	1	0
X Coordinate MSB	■	■	[colour: dark green]	[colour: dark green]	[colour: dark green]	[colour: dark green]	[colour: dark green]	[colour: dark green]	[colour: dark green]	•	Layer 2 X Coordinate MSB
Reserved	■	■	[colour: dark green] 0	[colour: dark green] 0	[colour: dark green] 0	[colour: dark green] 0	[colour: dark green] 0	[colour: dark green] 0	[colour: dark green] 0	[colour: pink]	Reserved, must be 0

LSB is in **NextREG 22 (16h)**