#### [?]

[?]	R	W	7	6	5	4	3	2	1	0	Description	H	D
[?]	■	■	[colour: dark green]	[colour: dark green]	[colour: dark green]	[colour: dark green]	[colour: dark green]	[colour: dark green]	[colour: pink]	•	Status
[?]	■	■	[colour: dark green]	[colour: dark green]	[colour: dark green]	[colour: dark green]	[colour: dark green]	[colour: dark green]	•	[colour: pink]	Status
[?]	■	■	[colour: dark green] 0	[colour: dark green] 0	[colour: dark green] 0	[colour: dark green] 0	[colour: dark green] 0	[colour: dark green] 0	[colour: pink]	[colour: pink]	Reserved must be 0

[?]g, set bits indicate that the device generated an interrupt in the past or an in-\ [?]nding\ [?], set bits clear the status. In Hardware IM2 mode, the status will continue be-\ [?]set until the interrupt pending condition is cleared #### [?]C9h) – Interrupt Status 1

[?]	R	W	Data Bits								Description	H	D
			7	6	5	4	3	2	1	0
[?]	■	■	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	•	Status
[?]	■	■	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	•	[colour: pink]	Status
[?]	■	■	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	•	[colour: pink]	[colour: pink]	Status
[?]	■	■	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	•	[colour: pink]	[colour: pink]	[colour: pink]	Status
[?]	■	■	[colour: pink]	[colour: pink]	[colour: pink]	•	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	Status
[?]	■	■	[colour: pink]	[colour: pink]	•	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	Status
[?]	■	■	[colour: pink]	•	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	Status
[?]	■	■	•	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	Status

[?]g, set bits indicate that the device generated an interrupt in the past or an in-\ [?]nding\ [?], set bits clear the status. In Hardware IM2 mode, the status will continue be-\ [?]set until the interrupt pending condition is cleared #### [?]CAh) – Interrupt Status 2

[?]	R	W	Data Bits								Description	H	D
			7	6	5	4	3	2	1	0
[?]	■	■	[colour: dark green]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: dark green]	[colour: pink]	[colour: pink]	•	Status		0
[?]	■	■	[colour: dark green]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: dark green]	[colour: pink]	•	[colour: pink]	Status		0
[?]	■	■	[colour: dark green]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: dark green]	•	[colour: pink]	[colour: pink]	Status		0
[?]	■	■	[colour: dark green]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: dark green] 0	[colour: pink]	[colour: pink]	[colour: pink]	Reserved, must be 0		0
[?]	■	■	[colour: dark green]	[colour: pink]	[colour: pink]	•	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	Status		0
[?]	■	■	[colour: dark green]	[colour: pink]	•	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	Status		0
[?]	■	■	[colour: dark green]	•	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	Status		0
[?]	■	■	[colour: dark green] 0	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	Reserved, must be 0		0

[?]upt\ [?]upt\ [?]g, set bits indicate that the device generated an interrupt in the past or an in-\ [?]nding\ [?], set bits clear the status. In Hardware IM2 mode, the status will continue be-\ [?]set until the interrupt pending condition is cleared #### [?]CBh) – Reserved

[?]	R	W	Data Bits								Description	H	D
			7	6	5	4	3	2	1	0
[?]	■	■	[colour: dark green] 1	[colour: dark green] 1	[colour: dark green] 1	[colour: dark green] 1	[colour: dark green] 1	[colour: dark green] 1	[colour: dark green] 1	[colour: dark green]	Reserved, must be 1

[?]Fh) #### [?]CCh) – DMA Interrupt Enables 0

[?]	R	W	Data Bits								Description	H	D
			7	6	5	4	3	2	1	0
[?]	■	■	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	•	1 to enable		0
[?]	■	■	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	•	[colour: pink]	1 to enable		0
[?]	■	■	•	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	1 to enable		0

[?]ate the corresponding interrupt will interrupt a DMA operation when in Hard-\ [?]ode #### [?]CDh) – DMA Interrupt Enables 1

[?]	R	W	Data Bits								Description	H	D
			7	6	5	4	3	2	1	0
[?]	■	■	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	•	1 to enable		0
[?]	■	■	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	•	[colour: pink]	1 to enable		0
[?]	■	■	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	•	[colour: pink]	[colour: pink]	1 to enable		0
[?]	■	■	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	•	[colour: pink]	[colour: pink]	[colour: pink]	1 to enable		0
[?]	■	■	[colour: pink]	[colour: pink]	[colour: pink]	•	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	1 to enable		0
[?]	■	■	[colour: pink]	[colour: pink]	•	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	1 to enable		0
[?]	■	■	[colour: pink]	•	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	1 to enable		0
[?]	■	■	•	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	1 to enable		0

[?]ate the corresponding interrupt will interrupt a DMA operation when in Hard-\ [?]ode #### [?]CEh) – DMA Interrupt Enables 2

[?]	R	W	Data Bits								Description	H	D
			7	6	5	4	3	2	1	0
[?]	■	■	[colour: dark green]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: dark green]	[colour: pink]	[colour: pink]	•	1 to enable		0
[?]	■	■	[colour: dark green]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: dark green]	[colour: pink]	•	[colour: pink]	1 to enable		0
[?]	■	■	[colour: dark green]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: dark green]	•	[colour: pink]	[colour: pink]	1 to enable		0
[?]	■	■	[colour: dark green]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: dark green] 0	[colour: pink]	[colour: pink]	[colour: pink]	Reserved, must be 0		0
[?]	■	■	[colour: dark green]	[colour: pink]	[colour: pink]	•	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	1 to enable		0
[?]	■	■	[colour: dark green]	[colour: pink]	•	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	1 to enable		0
[?]	■	■	[colour: dark green]	•	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	1 to enable		0
[?]	■	■	[colour: dark green] 0	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	Reserved, must be 0		0

[?]ate the corresponding interrupt will interrupt a DMA operation when in Hard-\ [?]ode #### [?]

Group Name	R	W	7	6	5	4	3	2	1	0	Description	H	D
Reserved, write 0	■	■	[colour: dark green] 0	[colour: dark green] 0	[colour: dark green] 0	[colour: dark green] 0	[colour: dark green] 0	[colour: dark green] 0	[colour: dark green] 0	[colour: dark green] 0	Reserved, must be 0

\* Write **0 (00h)** > Since interrupts are only sampled at the end of an instruction by the Z80N, each time the DMA is interrupted, one instrucion of progress is made in the main program #### NextREG 216 (D8h) – I/O Traps (Experimental)

Group Name	R	W	Data Bits								Description	H	D
			7	6	5	4	3	2	1	0
+3 FDC	■	■	[colour: dark green]	[colour: dark green]	[colour: dark green]	[colour: dark green]	[colour: dark green]	[colour: dark green]	[colour: dark green]	•	1 to enable on ports 2FFDh and 3FFDh		0
Reserved	■	■	[colour: dark green] 0	[colour: dark green] 0	[colour: dark green] 0	[colour: dark green] 0	[colour: dark green] 0	[colour: dark green] 0	[colour: dark green] 0	[colour: pink]	Reserved, must be 0

\* An I/O trap generates a Multiface NMI and is indicated in **NextREG 2 (02h)**\ Traps cannot be triggered by the DMA or while the Multiface, divMMC or external NMI is active #### NextREG 217 (D9h) – I/O Traps Write (Experimental)

Group Name	R	W	Data Bits								Description	H	D
			7	6	5	4	3	2	1	0
Data	■	■	•	•	•	•	•	•	•	•	8-bit value

Holds data written during trapped I/O write cycle #### NextREG 218 (DAh) – I/O Trap Cause (Experimental)

Group Name	R	W	Data Bits								Description	H	D
			7	6	5	4	3	2	1	0
I/O Trap Cause	■	■	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	0	0	None – 0 at the time NR 02 (02h) D4 is 0
			[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	0	1	Port 2FFDh read
			[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	1	0	Port 3FFDh read
			[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	1	1	Port 3FFDh write

\* If **NextREG 02 (02h):D4** indicates that an I/O cycle was trapped, this register indicates the cause #### NextREG 240 (F0h) – XDEV (Issue 4 ZX Spectrum Next Only)

Group Name	R	W	Data Bits								Description	H	D
			7	6	5	4	3	2	1	0
Select Mode*	■		1	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	Select Mode Enabled		1
Currently Selected Device	■		[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	0	0	none
			[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	0	1	Xilinx™ DNA (See [colour: pale green] below)
			[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	1	0	Xilinx™ XADC (See [colour: lavender] below)
Select Device*		■	1	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	Enter Select Mode
			0	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	Enter Selected Device Mode
			[colour: pink]	1	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	Change Selected Device
No Device Selected		■	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	0	0	none
[colour: pale green] DNA	[colour: pale green] ■	[colour: pale green]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pale green] •	[colour: pale green] DNA bit (serial stream shifts left)¹
[colour: pale green] SELECT / DNA RELOAD	[colour: pale green]	[colour: pale green] ■	[colour: pale green] 1	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pale green] Enter Select Mode or DNA string reload
[colour: lavender] BUSY	[colour: lavender] ■	[colour: lavender]	[colour: pink]	[colour: lavender] 1	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: lavender] 1 if XADC busy with conversion
[colour: lavender] EOC	[colour: lavender] ■	[colour: lavender]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: lavender] 1	[colour: pink]	[colour: lavender] 1 if XADC conv. complete since last read²
[colour: lavender] EOS	[colour: lavender] ■	[colour: lavender]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: lavender] 1	[colour: lavender] 1 if XADC conv. seq. comp. since last read²
[colour: lavender] SELECT	[colour: lavender]	[colour: lavender] ■	[colour: lavender] 1	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: lavender] Enter Select Mode
[colour: lavender] XADC RESET	[colour: lavender]	[colour: lavender] ■	[colour: pink]	[colour: lavender] 1	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: lavender] 1 to reset XADC
[colour: lavender] XADC CONVST	[colour: lavender]	[colour: lavender] ■	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: lavender] 1	[colour: lavender] 1 to start conversion

\* Re-enter Select Mode at any time by writing to the register with **D7** set\ Select a device to communicate with by writing to the register with **D7:D6** set then exit Select Mode by clearing **D7**. Thereafter the particular device is attached to the NextREG\ 1 The first eight bits read will indicate the length of the following DNA bits\ 2 Read clears #### NextREG 248 (F8h) – XADC Register\* (Issue 4 ZX Spectrum Next Only)

Group Name	R	W	Data Bits								Description	H	D
			7	6	5	4	3	2	1	0
DADDR	■	■	[colour: pink]	•	•	•	•	•	•	•	XADC DRP register address value	■	0
XADC DRP port read/write mode**	■	■	0	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	[colour: pink]	Initiate read from XADC DRP port
			1								Initiate write to XADC DRP port

\* An XADC Register read or write is initiated by writing to this register\ Before initiating a write, store the value in **NextREG 249 (F9h)** and **NextREG 250 (FAh)** first\ There must be at least **six 28 MHz** cycles after each read or write initiation before the action is completed\ \*\* Reads as **0** #### NextREG 249 (F9h) – XADC D0 (Issue 4 ZX Spectrum Next Only)

Group Name	R	W	Data Bits								Description	H	D
			7	6	5	4	3	2	1	0
DRP Data Bus LSB (D7:D0)	■	■	•	•	•	•	•	•	•	•	Data	■	0

\* DRP reads store result here and DRP writes take value from here #### NextREG 250 (FAh) – XADC D1 (Issue 4 ZX Spectrum Next Only)

Group Name	R	W	Data Bits								Description	H	D
			7	6	5	4	3	2	1	0
DRP Data Bus MSB (D15:D8)	■	■	•	•	•	•	•	•	•	•	Data	■	0

\* DRP reads store result here and DRP writes take value from here #### NextREG 255 (FFh) - Reserved (Internal Use Only)