### The ZX Spectrum Next Hardware Ports List **NOTE** The following Hardware Ports are not listed:\ **ULA 254 (FEh), Legacy Memory Paging 3765 (7FFDh), 8189 (1FFDh), 57341 (DFFDh), 61431 (EFF7h), Layer 2 4667 (123Bh) and ULAplus 65339 (FF3Bh) / 48955 (BF3B)**\ Ports are arranged according to their function.\ Please also consult the **ports.txt** document found in your **System/Next™** distribution for a complete list of ports ### Input / Output / Legacy Video #### Port 255 (FFh) – Timex SCLD ULA Extensions\*
Group NameRWData BitsDescription
76543210
Screen Mode Select■■000Std: DFILE0+COLOURFILE0 @ 4000h
001Shd: DFILE1+COLOURFILE1 @ 6000h
010HC: DFILE @ 4000h, COLOURFILE @ 6000h
110HR: even DFILE @ 4000h, odd DFILE @6000h
HiRes Colour Scheme Select■■000BRIGHT Black on White
001BRIGHT Blue on Yellow
010BRIGHT Red on Cyan
011BRIGHT Magenta on Green
100BRIGHT Green on Magenta
101BRIGHT Cyan on Red
110BRIGHT Yellow on Blue
111BRIGHT White on Black
Frame Interrrupt Control■■•1 to Disable ULA Frame Interrupt
Timex MMU Select¹■■•Timex Horizontal MMU Bank Select
\* Only readable if **NR 8 (08h):D2** = **1**\ ¹ Not implemented on the ZX Spectrum Next #### Port 64479 (FBDFh) – Kempston Mouse X position
Group NameRWData BitsDescription
76543210
Current X Position■••••••••Value 0 – 255*
\* Returns the current X position of the mouse **0 - 255**.\ The value wraps from **255** to **0** on a right movement and from **0** to **255** on a left movement. #### Port 65503 (FFDFh) – Kempston Mouse Y position
Group NameRWData BitsDescription
76543210
Current Y Position■••••••••Value 0 - 255*
\* Returns the current Y position of the mouse **0 - 255**.\ The value decrements and wraps from **255** to **0** on a downward movement and increments and wraps from **0** to **255** on an upward movement. #### Port 64223 (FADFh) – Kempston Mouse Button Status
Group NameRWData BitsDescription
76543210
Mouse Button Flags¹■•Left Mouse button status
•Right Mouse button status
•Middle Mouse button status
Mouse Wheel Position²■••••Mouse Wheel position (Wraps)
¹ Pressed = **1**, Not Pressed = **0**\ ² Value **0** to **15**. Upwards scroll **15** to **0** – wraps to **15**; Downards scroll **0** to **15** – wraps to **0** #### Port 31 (1Fh) – Kempston Joystick 1 / Mega Drive Pad 1 Status
Group NameRWData BitsDescription
76543210
Joystick Movement Status■•Right (pin 4)
•Left (pin 3)
•Down (pin 2)
•Up (pin 1)
Joystick Button Status■•Fire 1 (MD = B) (pin 6)
•Fire 2 (MD = C) (pin 9)
•MD = A (0 on Kempston)
•MD Start (0 on Kempston)
Joystick ports can be placed in I/O mode via NR 11 (0Bh)\ Kempston joysticks and Mega Drive Pads share ports but MD pads use more bits\ The X/Y/Z buttons on MD pads can be read via NR 178 (B2h)\ All twelve MD pad buttons can be assigned to the keyboard – See NR 05 (05h)\ When using an MD pad in more limited joystick modes, the excess buttons can generate keypresses if so programmed #### Port 55 (37h) – Kempston Joystick 2 / Mega Drive Pad 2 Status
Group NameRWData BitsDescription
76543210
Joystick Movement Status■•Right (pin 4)
•Left (pin 3)
•Down (pin 2)
•Up (pin 1)
Joystick Button Status■•Fire 1 (MD = B) (pin 6)
•Fire 2 (MD = C) (pin 9)
•MD = A (0 on Kempston)
•MD Start (0 on Kempston)
Joystick ports can be placed in I/O mode via NR 11 (0Bh)\ Kempston joysticks and Mega Drive Pads share ports but MD pads use more bits\ The X/Y/Z buttons on MD pads can be read via NR 178 (B2h)\ All twelve MD pad buttons can be assigned to the keyboard – See NR 05 (05h)\ When using an MD pad in more limited joystick modes, the excess buttons can generate keypresses if so programmed ### Audio #### Port 65533 (FFFDh) – PSG Control and Register Select
Group NameRWData BitsDescription
76543210
Selected Register Status■••••••••Value in selected register of active PSG
Active PSG Control■00Reserved
11PSG 0 made active*
10PSG 1 made active
01PSG 2 made active
Stereo Channel Control¹■1Reserved, must be 1
1Reserved, must be 1
1Reserved, must be 1
•Right Channel Enable
•Left Channel Enable
1Reserved, must be 1
Register Select²••••If 0000 selects a register from the Active PSG
\* Default value\ ¹ If **NR 8 (08h):D1** = **1** and **D7** through **D4** are not **0000** #### Port 49149 (BFFDh) – PSG Data
Group NameRWData BitsDescription
76543210
Selected Register Status¹■••••••••Value in selected register of active PSG
Active PSG Register Data■••••••••Value to write to the register
¹ Readable if machine type is ZX Spectrum Next or ZX Spectrum +3 only. #### Port 49141 (BFF5h) – PSG Info
Group NameRWData BitsDescription
76543210
Currently selected PSG register■•••••Value of selected register of active PSG
Reserved■•Reserved
Active PSG■11PSG 0 is active
10PSG 1 is active
01PSG 2 is active
#### Ports 251¹, 223², 31³, 241⁴, 63⁵ (FBh, DFh, 1Fh, F1h, 3Fh) – DAC Channel A (Left)
Group NameRWData BitsDescription
76543210
DAC output■••••••••8-bit unsigned sample value
All DACs originate from various ZX Spectrum peripherals and compatible models and are kept for compatibility. DACs are enabled by setting **NR 8 (08h):D3** = **1**\ ¹ Found in Pentagon and ATM\ ² Found in SpecDRUM™\ ³ Found in SoundDrive 1\ ⁴ Found in SoundDrive 2\ ⁵ Found in Profi Covox #### Ports 179¹, 15², 243³ (B3h, 0Fh, F3h) – DAC Channel B (Left)
Group NameRWData BitsDescription
76543210
DAC output■••••••••8-bit unsigned sample value
All DACs originate from various ZX Spectrum peripherals and compatible models and are kept for compatibility. DACs are enabled by setting **NR 8 (08h):D3** = **1**\ ¹ Found in GS Govox\ ² Found in SoundDrive 1 and Covox\ ³ Found in SoundDrive 2 #### Ports 179¹, 79², 249³ (B3h, 4Fh, F9h) – DAC Channel C (Right)
Group NameRWData BitsDescription
76543210
DAC output■••••••••8-bit unsigned sample value
All DACs originate from various ZX Spectrum peripherals and compatible models and are kept for compatibility. DACs are enabled by setting **NR 8 (08h):D3** = **1**\ ¹ Found in GS Govox\ ² Found in SoundDrive 1 and Covox\ ³ Found in SoundDrive 2 #### Ports 251¹, 223², 95³ (FBh, DFh, 5Fh) – DAC Channel D (Right)
Group NameRWData BitsDescription
76543210
DAC output■••••••••8-bit unsigned sample value
All DACs originate from various ZX Spectrum peripherals and compatible models and are kept for compatibility. DACs are enabled by setting **NR 8 (08h):D3** = **1**\ ¹ Found in Pentagon, ATM and SoundDrive 2\ ² Found in SpecDRUM™\ ³ Found in SoundDrive 1 and Profi Covox ### Storage #### Port 227 (E3h) – divMMC Control
Group NameRWData BitsDescription
76543210
RAM bank Control■■••••Memory Bank Select for 8K - 16K region
MapRAM Control¹■■•MapRAM Enable
ConMEM Control²■■•ConMEM Enable
¹ Can only be set once. On the original divMMC only a power cycle can reset it. The ZX Spectrum Next implementation uses **NR 9 (09h)** where **D3** can be set,in order to reset this bit. When set, it replaces the expected esxDOS ROM with divMMC RAM bank **3**\ ² Can be used to manually control divMMC mapping. When set it maps in divMMC; **0K - 8K** will contain the esxDOS ROM, **8K - 16K** will contain the selected divMMC bank (from **D0** through **D3**). The divMMC automatically maps itself in when instruction fetches hit specific addresses in the ROM. When this happens, the esxDOS ROM (or divMMC bank **3** if mapRAM is set) appears in **0K - 8K** and the selected divMMC bank appears as RAM in **8K - 16K**. DivMMC automapping is normally disabled by NextZXOS. See **NR 6 (06h):D4**. The divMMC has been enhanced, in order to add entry points and make them programmable.