cause the CPU is given a new window in to a different bank in physical memory. This way the usable physical memory can far exceed the memory the CPU can normally see while, at the same time, older software is completely unaware and will continue to run properly without performing any bank switching. ### Memory Management There are two banking schemes employed in the ZX Spectrum Next: Standard and MMU-based banking. The Standard scheme is inherited from the +3 and the other 128K Spectrum models. The MMU scheme co-exists with the Standard scheme but it is unique to the ZX Spectrum Next.  ``` ROM RAM +----------------+----------------+----------------+----------------+ | 16K | 16K | 16K | 16K | +----------------+----------------+----------------+----------------+ 00000 16384 32768 49152 65535 0000h 4000h 8000h C000h FFFFh ``` *Fig. 46 – Standard (NextBASIC) memory map* As you can see, in the memory map *NextBASIC* uses, the available 64K of addressable memory is divided into four slots of 16K each with the bottom slot always occupied by ROM. Standard banking, inherited from prior Spectrum models, selects which 16K ROM is visible in the bottom 16K slot (addresses 0 to 16383) and which 16K RAM bank is visible in the top 16K slot (addresses 49152 to 65535). The Spectrum +3 introduced a new, so called, **allRAM** mode that could place a limited selection of arrangements of four 16K RAM banks into all four slots. This was not widely used and is often forgotten by programmers who mostly target the 128K Spectrum models prior to the +3. A good example of **allRAM** mode is running CP/M, that requires RAM at the bottom of the address map. There is a total of four 16K ROMs to select from (inherited from the +3) and a total of **48** 16K RAM banks available (**112** in **2048K** ZX Spectrum Nexts). If you make a quick calculation, that accounts for **832K** in the unexpanded Issue 2 ZX Spectrum Next. The remaining portion of the **1024K** is allocated to other uses, most notably to divMMC memory. The *NextZXOS Startup menu* reports available RAM only, which will be either **768K** or **1792K**. The Standard banking scheme is controlled by hardware I/O ports (covered in the previous chapter) and via the **BANK** command and its variants which we will examine soon. The MMU (memory management unit) scheme is diagrammed below. It is much more flexible in that it can map any **8K** bank of physical RAM into any **8K** slot of the CPU's addressable memory.  ``` 8192 24576 40960 57344 2000h 6000h A000h E000h +--------+--------+--------+--------+--------+--------+--------+--------+ | MMU0 | MMU1 | MMU2 | MMU3 | MMU4 | MMU5 | MMU6 | MMU7 | +--------+--------+--------+--------+--------+--------+--------+--------+ 00000 16384 32768 49152 65535 0000h 4000h 8000h C000h FFFFh ``` *Fig. 47 – MMU based memory map*