| Bits | Description |
|---|---|
| 7 | 1 if the reset signal to the expansion bus and esp is asserted |
| 6:5 | Reserved |
| 4 | 1 if multiface nmi was generated by an i/o trap (experimental, see nextreg 0xDA) |
| 3 | 1 if multiface nmi was generated by this nextreg |
| 2 | 1 if divmmc nmi was generated by this nextreg |
| 1 | 1 if the last reset was a hard reset* |
| 0 | 1 if the last reset was a soft reset* |
* Only one of bits 1:0 will be set
| Bits | Description |
|---|---|
| 7 | Assert and hold reset to the expansion bus and the esp wifi (hard reset = 0) |
| 6:5 | Reserved must be zero |
| 4 | Clear i/o trap (write zero to clear) (experimental)** |
| 3 | Generate multiface nmi (write zero to clear)** |
| 2 | Generate divmmc nmi (write zero to clear)** |
| 1 | Generate a hard reset (reboot)* |
| 0 | Generate a soft reset* |
* Hard reset has precedence
** These signals are ignored if the multiface, divmmc, dma or external nmi master is active
** Copper cannot clear these bits
** An i/o trap could occur at the same time as mf / divmmc cause; always check this bit in nmi isr if important