0000 1000 = EMULATORS 0000 1010 = ZX Spectrum Next 1111 1010 = ZX Spectrum Next Anti-brick 1001 1010 = ZX Spectrum Next Core on UnAmiga Reloaded 1010 1010 = ZX Spectrum Next Core on UnAmiga 1011 1010 = ZX Spectrum Next Core on SiDi 1100 1010 = ZX Spectrum Next Core on MIST 1101 1010 = ZX Spectrum Next Core on MiSTer 1110 1010 = ZX Spectrum Next Core on ZX-DOS
| Bits | Description |
|---|---|
| 7 | 1 if the reset signal to the expansion bus and esp is asserted |
| 6:5 | Reserved |
| 4 | 1 if multiface nmi was generated by an i/o trap (experimental, see nextreg 0xDA) |
| 3 | 1 if multiface nmi was generated by this nextreg |
| 2 | 1 if divmmc nmi was generated by this nextreg |
| 1 | 1 if the last reset was a hard reset* |
| 0 | 1 if the last reset was a soft reset* |
* Only one of bits 1:0 will be set
| Bits | Description |
|---|---|
| 7 | Assert and hold reset to the expansion bus and the esp wifi (hard reset = 0) |
| 6:5 | Reserved must be zero |
| 4 | Clear i/o trap (write zero to clear) (experimental)** |
| 3 | Generate multiface nmi (write zero to clear)** |
| 2 | Generate divmmc nmi (write zero to clear)** |
| 1 | Generate a hard reset (reboot)* |
| 0 | Generate a soft reset* |
* Hard reset has precedence
** These signals are ignored if the multiface, divmmc, dma or external nmi master is active
** Copper cannot clear these bits
** An i/o trap could occur at the same time as mf / divmmc cause; always check this bit in nmi isr if important
| Bits | Description |
|---|---|
| 7 | nextreg 0x44 second byte indicator |
| 6:4 | Display timing |
| 3 | User lock on display timing applied |
| 2-0 | Machine type |
| Bits | Description |
|---|---|
| 7 | 1 to allow changes to bits 6:4 |
| 6:4 | Selects display timing affects port decoding and contention 000 = Internal Use 001 = ZX 48K display timing 010 = ZX 128K/+2 display timing 011 = ZX +2A/+2B/+3 display timing 100 = Pentagon display timing (changes to 50 Hz) |
| 3 | 1 to toggle user lock on display timing (hard reset = 0) |
| 2:0 | Selects machine type (config mode only) determines roms loaded 000 = Configuration mode 001 = ZX 48K 010 = ZX 128K/+2 011 = ZX +2A/+2B/+3 100 = Pentagon |
A write to this register disables the bootrom
| Bits | Description |
|---|---|
| 7:6 | Joystick 1 mode (LSB) |
| 5:4 | Joystick 2 mode (LSB) |
| 3 | Joystick 1 mode (MSB) |
| 2 | 50/60 Hz mode (0 = 50Hz, 1 = 60Hz, Pentagon forces 50Hz) |
| 1 | Joystick 2 mode (MSB) |
| 0 | Enable scandoubler (1 = enabled for vga, 0 for crt) |
Joystick modes: 000 = Sinclair 2 (12345) 001 = Kempston 1 (port 0x1F) 010 = Cursor (56780) 011 = Sinclair 1 (67890) 100 = Kempston 2 (port 0x37) 101 = MD 1 (3 or 6 button joystick port 0x1F) 110 = MD 2 (3 or 6 button joystick port 0x37) 111 = User Defined Keys Joystick on nextreg 0x28, nextreg 0x29 and nextreg 0x2B: 1. Write 128 to nextreg 0x28 2. Write 0 (left joystick) or 16 (right joystick) to nextreg 0x29 3. Write twelve bytes to nextreg 0x2B in order. The bytes correspond to the twelve buttons on an md pad (MODE=11 X Z Y START A C B U D L R=0) 4. Each byte written identifies a key in the 8x7 membrane; bits 5:3 select the row and bits 2:0 select the column with 111 meaning no action generate key input if so programmed
* Joysticks can be placed in i/o mode via nextreg 0x0B
* Programming the user defined keys joystick is done through the ps2 keymap interface
* In kempston and md modes, excess buttons on a controller not read via ports will
| Bits | Description |
|---|---|
| 7 | Enable F8 cpu speed hotkey and F5/F6 expansion bus hotkeys (soft reset = 1) |
| 6 | Divert BEEP only to internal speaker (hard reset = 0) |
| 5 | Enable F3 50/60 Hz hotkey (soft reset = 1) |
| 4 | Enable divmmc nmi by DRIVE button (hard reset = 0) |
| 3 | Enable multiface nmi by M1 button (hard reset = 0) |
| 2 | PS/2 mode (0 = keyboard primary, 1 = mouse primary; config mode only) |
| 1-0 | Audio chip mode (00 = YM, 01 = AY, 10 = ZXN-8950, 11 = Hold all AY in reset) |
| Bits | Description |
|---|---|
| 7 | Unlock port 0x7ffd (read 1 indicates port 0x7ffd is not locked) |
| 6 | Disable ram and port contention (soft reset = 0) |
| 5 | AY stereo mode (0 = ABC, 1 = ACB) (hard reset = 0) |
| 4 | Enable internal speaker (hard reset = 1) |
| 3 | Enable 8-bit DACs (A,B,C,D) (hard reset = 0) |
| 2 | Enable port 0xff Timex video mode read (hides floating bus on 0xff) (hard reset = 0) |
| 1 | Enable turbosound (currently selected AY is frozen when disabled) (hard reset = 0) |
| 0 | Implement issue 2 keyboard (hard reset = 0) |
| Bits | Description |
|---|---|
| 7 | Place AY 2 in mono mode (hard reset = 0) |
| 6 | Place AY 1 in mono mode (hard reset = 0) |
| 5 | Place AY 0 in mono mode (hard reset = 0) |
| 4 | Sprite id lockstep (nextreg 0x34 and port 0x303B are in lockstep) (soft reset = 0) |
| 3 | Reset divmmc mapram bit (port 0xe3 bit 6) (read returns 0) |
| 2 | 1 to silence hdmi audio (hard reset = 0) |
| 1:0 | Scanline weight 00 = scanlines off 01 = scanlines 50% 10 = scanlines 25% 11 = scanlines 12.5% |
| Bits | Description |
|---|---|
| 7:6 | Multiface type (hard reset = 00) (config mode only) 00 = Multiface +3 (enable port 0x3F, disable port 0xBF) 01 = Multiface 128 v87.2 (enable port 0xBF, disable port 0x3F) 10 = Multiface 128 v87.12 (enable port 0x9F, disable port 0x1F) 11 = Multiface 1 (enable port 0x9F, disable port 0x1F) |
| 5 | Reserved, must be zero |
| 4 | Enable divmmc automap (hard reset = 0) |
| 3 | 1 to reverse left and right mouse buttons (hard reset = 0) |
| 2 | Reserved, must be zero |
| 1:0 | mouse dpi (hard reset = 01) 00 = low dpi 01 = default 10 = medium dpi 11 = high dpi |
| Bits | Description |
|---|---|
| 7 | 1 to enable i/o mode |
| 6 | Reserved, must be 0 |
| 5:4 | I/O Mode 00 = bit bang 01 = clock 10 = uart on left joystick port 11 = uart on right joystick port |
| 3:1 | Reserved, must be 0 |
| 0 | Parameter bit bang : copied to pin 7 clock : 0 = hold high when clock becomes high, 1 = run * uart : 0 = redirect esp uart0 to joystick, 1 = redirect pi uart1 to joystick (Tx out on pin 7, Rx in from pin 9, CTS_n in from pin 6 **) |
* CTC channel 3 is currently used to drive pin 7 in clock mode. Freq = Fctc3 / 2.
** CTS_n is only active if the seleced uart is in hw flow control mode.
The state of output pin 7 is stored internally in a register and is retained across changing modes and while i/o mode is disabled. While in i/o mode, keyboard joystick types (Sinclair, Cursor, etc) produce no readings but the current state of pins can still be read via the Kempston ports. When leaving i/o mode, joystick operation resumes after ~64 scan lines have passed.
| Bits | Description |
|---|---|
| 7:4 | Reserved, 0 |
| 3:0 | Board ID 0000 = ZXN Issue 2, XC6SLX16-2FTG256, 128Mbit W25Q128JV, 24bit spi, 64K*8 core size 0001 = ZXN Issue 3, XC6SLX16-2FTG256, 128Mbit W25Q128JV, 24bit spi, 64K*8 core size 0010 = ZXN Issue 4, XC7A15T-1CSG324, 256Mbit MX25L25645G, 32bit spi, 64K*34 core size |
| Bits | Description |
|---|---|
| 7 | Reserved |
| 6:2 | Cored ID |
| 1 | Button DRIVE (divmmc) is pressed |
| 0 | Button M1 (multiface) is pressed |
| Bits | Description |
|---|---|
| 7 | Start selected core |
| 6:5 | Reserved, must be 0 |
| 4:0 | Core ID 0-31 (config mode only)* |
* A write of an out of range core id is ignored; this is the preferred way to determine max id
| Bits | Description |
|---|---|
| 7:3 | Reserved, must be 0 |
| 2:0 | Mode (VGA = 0..6, HDMI = 7) 000 = Base VGA timing, clk28 = 28000000 \ HDMI compatible 001 = VGA setting 1, clk28 = 28571429 / HDMI compatible 010 = VGA setting 2, clk28 = 29464286 011 = VGA setting 3, clk28 = 30000000 100 = VGA setting 4, clk28 = 31000000 101 = VGA setting 5, clk28 = 32000000 110 = VGA setting 6, clk28 = 33000000 |
* 50/60Hz selection depends on bit 2 of nextreg 0x05
Writable in config mode only.
| Bits | Description |
|---|---|
| 7:0 | Transparency colour value (soft reset = 0xe3) |
* Note: This value is 8-bit, so the transparency colour is compared against the MSB bits of the final 9-bit colour only.
* Note: This colour only applies to Layer 2, ULA and LoRes. Sprites use nextreg 0x4B and the tilemap uses nextreg 0x4C for transparency except in text mode
| Bits | Description |
|---|---|
| 7 | Enable lores mode (soft reset = 0) |
| 6 | Sprite priority (1 = sprite 0 on top, 0 = sprite 127 on top) (soft reset = 0) |
| 5 | Enable sprite clipping in over border mode (soft reset = 0) |
| 4:2 | Set layer priority (eg SLU = sprites over layer 2 over ula) (soft reset = 000) 000 - S L U 001 - L S U 010 - S U L 011 - L U S 100 - U S L 101 - U L S 110 - (U|T)S(T|U)(B+L) Blending layer and Layer 2 combined, colours clamped to [0,7] 111 - (U|T)S(T|U)(B+L-5) Blending layer and Layer 2 combined, colours clamped to [0,7] |
| 1 | Enable sprites over border (soft reset = 0) |
| 0 | Enable sprites (soft reset = 0) |
| Bits | Description |
|---|---|
| 7:0 | Clip window coordinate (inclusive) |
1st write - X1 position (soft reset = 0) 2nd write - X2 position (soft reset = 255) 3rd write - Y1 position (soft reset = 0) 4rd write - Y2 position (soft reset = 191) Reads do not advance the clip position When the clip window is enabled for sprites in "over border" mode, the X coords are internally doubled and the clip window origin is moved to the sprite origin inside the border.
| Bits | Description |
|---|---|
| 7:0 | Clip window coordinate (inclusive)* |
* LoRes may get a separate clip window in the future
1st write = X1 position (soft reset = 0) 2nd write = X2 position (soft reset = 255) 3rd write = Y1 position (soft reset = 0) 4rd write = Y2 position (soft reset = 191) Reads do not advance the clip position
| Bits | Description |
|---|---|
| 7:0 | Clip window coordinate (inclusive) |
1st write = X1 position (soft reset = 0) 2nd write = X2 position (soft reset = 159) 3rd write = Y1 position (soft reset = 0) 4rd write = Y2 position (soft reset = 255) Reads do not advance the clip position The X coordinates are internally doubled.
| Bits | Description |
|---|---|
| 7 | (R) Indicates if the ula is asserting an interrupt (even if disabled) |
| 7:3 | Reserved, must be 0 |
| 2 | Disables ula interrupt (soft reset = 0)** |
| 1 | Enables line Interrupt (soft reset = 0)** |
| 0 | MSB of line interrupt value (soft reset = 0) |
** Aliases of interrupt enable bits in nextreg 0xC4
| Bits | Description |
|---|---|
| 7 | Pattern address offset (add 128 to pattern address) |
| 6:0 | Sprite number 0-127, Pattern number 0-63 Selects which sprite has its attributes connected to the following registers. Effectively performs an out to port 0x303B with the same value |
| 7 | Ignored |
| 6:0 | Sprite number 0-127 Selects which sprite has its attributes connected to the following registers. |
If the sprite number is in lockstep with port 0x303B (nextreg 0x09 bit 4 is set) Otherwise Bit 7 always reads back as zero.
| Bits | Description |
|---|---|
| 7:0 | Select the palette index to change the associated colour. (soft reset = 0) PAPERs to indices 16-23 and Bright PAPERs to indices 24-31. a subset of indices 128-255. The number of active indices depends on the number of attribute bits assigned to INK and PAPER out of the attribute byte. |
For the ULA only, INKs are mapped to indices 0-7, Bright INKS to indices 8-15, In ULANext mode, INKs come from a subset of indices 0-127 and PAPERs come from In ULA+ mode, the top 64 entries hold the ula+ palette. The ULA always takes border colour from paper for standard ULA and ULAnext.
| Bits | Description |
|---|---|
| 7:0 | Colour for the palette index selected by nextreg 0x40. The format is RRRGGGBB - the lower blue bit of the 9-bit colour will be the logical OR of blue bits 1 and 0 of this 8-bit value. After the write, the palette index is auto-incremented to the next index if the auto-increment is enabled in nextreg 0x43. Reads do not auto-increment. Any other bits associated with the index will be zeroed. |
| Bits | Description |
|---|---|
| 7:0 | Mask indicating which bits of an attribute byte are used to represent INK. Other bits represent PAPER. (soft reset = 0x07) The mask can only indicate a solid sequence of bits on the right side of an attribute byte (1, 3, 7, 15, 31, 63, 127 or 255). INKs are mapped to base index 0 in the palette and PAPERs and border are mapped to base index 128 in the palette. The 255 value enables the full ink colour mode making all the palette entries INK. In this case PAPER and border are both taken from the fallback colour in nextreg 0x4A. If the mask is not one of those listed above, the INK is taken as the logical AND of the mask with the attribute byte and the PAPER and border colour are again both taken from the fallback colour in nextreg 0x4A. |
| Bits | Description |
|---|---|
| 7 | Disable palette write auto-increment (soft reset = 0) |
| 6-4 | Select palette for reading or writing (soft reset = 000) 000 = ULA first palette 100 = ULA second palette 001 = Layer 2 first palette 101 = Layer 2 second palette 010 = Sprites first palette 110 = Sprites second palette 011 = Tilemap first palette 111 = Tilemap second palette |
| 3 | Select Sprites palette (0 = first palette, 1 = second palette) (soft reset = 0) |
| 2 | Select Layer 2 palette (0 = first palette, 1 = second palette) (soft reset = 0) |
| 1 | Select ULA palette (0 = first palette, 1 = second palette) (soft reset = 0) |
| 0 | Enabe ULANext mode (soft reset = 0) |
| Bits | Description |
|---|---|
| 7:0 | RRRGGGBB |
| 7:1 | Reserved, must be 0 |
| 0 | lsb B If writing to an L2 palette |
| 7 | 1 for L2 priority colour, 0 for normal. An L2 priority colour moves L2 above all layers. If you need the same colour in both priority and normal modes, you will need to have two different entries with the same colour one with and one without priority. |
Two consecutive writes are needed to write the 9 bit colour 1st write: 2nd write: After two consecutive writes the palette index is auto-incremented if auto-increment is enabled in nextreg 0x43. Reads only return the 2nd byte and do not auto-increment. Writes to nextreg 0x40, 0x41, 0x43 reset to the 1st write.
| Bits | Description |
|---|---|
| 7:6 | Start control (soft reset = 00) 00 = Copper fully stopped 01 = Copper start, execute the list from index 0, and loop to the start 10 = Copper start, execute the list from last point, and loop to the start 11 = Copper start, execute the list from index 0, and restart the list when the raster reaches position (0,0) |
| 2:0 | Copper instruction memory address MSB (soft reset = 0) |
(Copper addresses range over 0 - 0x7FF = 2K) Writing the same start control value does not reset the copper
The 16-bit value is written in pairs. The first 8-bits are the MSB and are destined for an even copper instruction address. The second 8-bits are the LSB and are destined for an odd copper instruction address. After each write, the copper address is auto-incremented to the next memory position After a write to an odd address, the entire 16-bits is written to copper memory at once
| Bits | Description |
|---|---|
| 7:0 | Offset added to the vertical line counter affects copper, line interrupt and active line count. |
* Since a change in offset takes effect when the ula reaches row 0, the change can take up to
Normally the ula's pixel row 0 aligns with vertical line count 0. With a non-zero offset, the ula's pixel row 0 will align with the vertical line offset. Eg, if the offset is 32 then vertical line 32 will correspond to the first pixel row in the ula and vertical line 0 will align with the first pixel row of the tilemap and sprites. one frame to occur.
| Bits | Description |
|---|---|
| 7 | Disable ULA output (soft reset = 0) |
| 6:5 | Blending in SLU modes 6 & 7 (soft reset = 0) = 00 for ula as blend colour = 10 for ula/tilemap mix result as blend colour = 11 for tilemap as blend colour = 01 for no blending |
| 4 | Cancel entries in 8x5 matrix for extended keys |
| 3 | ULA+ enable (soft reset = 0) |
| 2 | ULA half pixel scroll (may change) (soft reset = 0) |
| 1 | Reserved, must be 0 |
| 0 | Enable stencil mode when both the ULA and tilemap are enabled (soft reset = 0) |
(if either are transparent the result is transparent otherwise the result is a logical AND of both colours)
| Bits | Description |
|---|---|
| 7 | 1 Enable the tilemap (soft reset = 0) |
| 6 | 0 for 40x32, 1 for 80x32 (soft reset = 0) |
| 5 | Eliminate the attribute entry in the tilemap (soft reset = 0) |
| 4 | Palette select (soft reset = 0) |
| 3 | Select textmode (soft reset = 0) |
| 2 | Reserved, must be 0 |
| 1 | Activate 512 tile mode (soft reset = 0) |
| 0 | Force tilemap on top of ULA (soft reset = 0) |
| Bits | Description |
|---|---|
| 7 | 1 to select bank 7, 0 to select bank 5 |
| 6 | Reserved, must be 0 |
| 5:0 | MSB of address of the tilemap in Bank 5 |
The value written into bits 5:0 is an offset into 16K bank 5 or 8K bank 7 allowing the tilemap to be placed at any multiple of 256 bytes. The value written here can be thought of as the MSB of an address in bank 5 0x40-0x7f or bank 7 0xc0-0xff. Because bank 7 is only 8K in size, addresses wrap across the 8K boundary instead of the 16K boundary.
| Bits | Description |
|---|---|
| 7 | 1 to select bank 7, 0 to select bank 5 |
| 6 | Reserved, must be 0 |
| 5:0 | MSB of address of tile definitions in Bank 5 |
The value written into bits 5:0 is an offset into 16K bank 5 or 8K bank 7 allowing the tile definitions to be placed at any multiple of 256 bytes. The value written here can be thought of as the MSB of an address in bank 5 0x40-0x7f or bank 7 0xc0-0xff. Because bank 7 is only 8K in size, addresses wrap across the 8K boundary instead of the 16K boundary.
| Bits | Description |
|---|---|
| 7 | 1 to enable the expansion bus |
| 6 | 1 to enable romcs rom replacement from divmmc banks 14/15 |
| 5 | 1 to disable i/o cycles & ignore iorqula |
| 4 | 1 to disable memory cycles & ignore romcs |
| 3 | 1 to enable the expansion bus |
| 2 | 1 to enable romcs rom replacement from divmmc banks 14/15 |
| 1 | 1 to disable i/o cycles & ignore iorqula |
| 0 | 1 to disable memory cycles & ignore romcs |
IMMEDIATE AFTER SOFT RESET (copied into bits 7-4)
| Bits | Description |
|---|---|
| 7 | 1 if ROMCS is asserted on the expansion bus (read only) |
| 6 | 1 to allow peripherals to override the ULA on some even port reads (rotronics wafadrive) |
| 5 | 1 to disable expansion bus nmi debounce (opus discovery) |
| 4 | 1 to propagate the max cpu clock at all times including when the expansion bus is off |
| 1-0 | max cpu speed when the expansion bus is on (currently fixed at 00 = 3.5MHz) |
0x85 ( 133 ) Internal Port Decoding Enables (0x85 is MSB) (soft reset if bit 31 = 1, hard reset if bit 31 = 0 : all 1) (0x85) | Bits | Description |
|---|---|
| 0 | port ff |
| 1 | port 7ffd |
| 2 | port dffd |
| 3 | port 1ffd |
| 4 | +3 floating bus |
| 5 | port 6b zxn dma |
| 6 | port 1f kempston / md1 |
| 7 | port 37 kempston 2 / md2 |
| 8 | port e3 divmmc control |
| 9 | multiface (two variable ports) |
| 10 | port 103b,113b i2c |
| 11 | port e7,eb spi |
| 12 | port 133b,143b,153b,163b uart |
| 13 | port fadf,fbdf,ffdf mouse (also disables kempston alias on port df) |
| 14 | port 57,5b,303b sprites |
| 15 | port 123b layer2 |
| 16 | port fffd,bffd ay |
| 17 | port 0f,1f,4f,5f dac soundrive mode 1 |
| 18 | port f1,f3,f9,fb dac soundrive mode 2 |
| 19 | port 3f,5f dac stereo profi covox |
| 20 | port 0f,4f dac stereo covox |
| 21 | port fb dac mono pentagon/atm (sd mode 2 off) |
| 22 | port b3 dac mono gs covox |
| 23 | port df dac mono specdrum, port 1f kempston alias |
| 24 | port bf3b,ff3b ula+ |
| 25 | port 0b z80 dma |
| 26 | port eff7 pentagon 1024 memory |
| 27 | port 183b,193b,1a3b,1b3b,1c3b,1d3b,1e3b,1f3b z80 ctc |
| 31 | register reset mode (soft or hard reset selection) |
0x89,0x88,0x87,0x86 (137-134) => Expansion Bus Decoding Enables (0x89 is MSB) (soft reset if bit 31 = 0, hard reset if bit 31 = 1 : all 1)
----- ----- ----- ... ----- The internal port decoding enables always apply. When the expansion bus is on, the expansion port decoding enables are logically ANDed with the internal enables. A zero bit indicates the internal device is disabled. If the expansion bus is on, this allows io cycles for disabled ports to propagate to the expansion bus, otherwise corresponding io cycles to the expansion bus are filtered.
0x84 ( 130 ) Internal Port Decoding Enables (0x85 is MSB) (soft reset if bit 31 = 1, hard reset if bit 31 = 0 : all 1) (0x84) | Bits | Description |
|---|---|
| 0 | port ff |
| 1 | port 7ffd |
| 2 | port dffd |
| 3 | port 1ffd |
| 4 | +3 floating bus |
| 5 | port 6b zxn dma |
| 6 | port 1f kempston / md1 |
| 7 | port 37 kempston 2 / md2 |
| 8 | port e3 divmmc control |
| 9 | multiface (two variable ports) |
| 10 | port 103b,113b i2c |
| 11 | port e7,eb spi |
| 12 | port 133b,143b,153b,163b uart |
| 13 | port fadf,fbdf,ffdf mouse (also disables kempston alias on port df) |
| 14 | port 57,5b,303b sprites |
| 15 | port 123b layer2 |
| 16 | port fffd,bffd ay |
| 17 | port 0f,1f,4f,5f dac soundrive mode 1 |
| 18 | port f1,f3,f9,fb dac soundrive mode 2 |
| 19 | port 3f,5f dac stereo profi covox |
| 20 | port 0f,4f dac stereo covox |
| 21 | port fb dac mono pentagon/atm (sd mode 2 off) |
| 22 | port b3 dac mono gs covox |
| 23 | port df dac mono specdrum, port 1f kempston alias |
| 24 | port bf3b,ff3b ula+ |
| 25 | port 0b z80 dma |
| 26 | port eff7 pentagon 1024 memory |
| 27 | port 183b,193b,1a3b,1b3b,1c3b,1d3b,1e3b,1f3b z80 ctc |
| 31 | register reset mode (soft or hard reset selection) |
0x89,0x88,0x87,0x86 (137-134) => Expansion Bus Decoding Enables (0x89 is MSB) (soft reset if bit 31 = 0, hard reset if bit 31 = 1 : all 1)
----- ----- ----- ... ----- The internal port decoding enables always apply. When the expansion bus is on, the expansion port decoding enables are logically ANDed with the internal enables. A zero bit indicates the internal device is disabled. If the expansion bus is on, this allows io cycles for disabled ports to propagate to the expansion bus, otherwise corresponding io cycles to the expansion bus are filtered.
0x83 ( 133 ) Internal Port Decoding Enables (0x85 is MSB) (soft reset if bit 31 = 1, hard reset if bit 31 = 0 : all 1) (0x83) | Bits | Description |
|---|---|
| 0 | port ff |
| 1 | port 7ffd |
| 2 | port dffd |
| 3 | port 1ffd |
| 4 | +3 floating bus |
| 5 | port 6b zxn dma |
| 6 | port 1f kempston / md1 |
| 7 | port 37 kempston 2 / md2 |
| 8 | port e3 divmmc control |
| 9 | multiface (two variable ports) |
| 10 | port 103b,113b i2c |
| 11 | port e7,eb spi |
| 12 | port 133b,143b,153b,163b uart |
| 13 | port fadf,fbdf,ffdf mouse (also disables kempston alias on port df) |
| 14 | port 57,5b,303b sprites |
| 15 | port 123b layer2 |
| 16 | port fffd,bffd ay |
| 17 | port 0f,1f,4f,5f dac soundrive mode 1 |
| 18 | port f1,f3,f9,fb dac soundrive mode 2 |
| 19 | port 3f,5f dac stereo profi covox |
| 20 | port 0f,4f dac stereo covox |
| 21 | port fb dac mono pentagon/atm (sd mode 2 off) |
| 22 | port b3 dac mono gs covox |
| 23 | port df dac mono specdrum, port 1f kempston alias |
| 24 | port bf3b,ff3b ula+ |
| 25 | port 0b z80 dma |
| 26 | port eff7 pentagon 1024 memory |
| 27 | port 183b,193b,1a3b,1b3b,1c3b,1d3b,1e3b,1f3b z80 ctc |
| 31 | register reset mode (soft or hard reset selection) |
0x89,0x88,0x87,0x86 (137-134) => Expansion Bus Decoding Enables (0x89 is MSB) (soft reset if bit 31 = 0, hard reset if bit 31 = 1 : all 1)
----- ----- ----- ... ----- The internal port decoding enables always apply. When the expansion bus is on, the expansion port decoding enables are logically ANDed with the internal enables. A zero bit indicates the internal device is disabled. If the expansion bus is on, this allows io cycles for disabled ports to propagate to the expansion bus, otherwise corresponding io cycles to the expansion bus are filtered.
0x82 ( 133 ) Internal Port Decoding Enables (0x85 is MSB) (soft reset if bit 31 = 1, hard reset if bit 31 = 0 : all 1) (0x82) | Bits | Description |
|---|---|
| 0 | port ff |
| 1 | port 7ffd |
| 2 | port dffd |
| 3 | port 1ffd |
| 4 | +3 floating bus |
| 5 | port 6b zxn dma |
| 6 | port 1f kempston / md1 |
| 7 | port 37 kempston 2 / md2 |
| 8 | port e3 divmmc control |
| 9 | multiface (two variable ports) |
| 10 | port 103b,113b i2c |
| 11 | port e7,eb spi |
| 12 | port 133b,143b,153b,163b uart |
| 13 | port fadf,fbdf,ffdf mouse (also disables kempston alias on port df) |
| 14 | port 57,5b,303b sprites |
| 15 | port 123b layer2 |
| 16 | port fffd,bffd ay |
| 17 | port 0f,1f,4f,5f dac soundrive mode 1 |
| 18 | port f1,f3,f9,fb dac soundrive mode 2 |
| 19 | port 3f,5f dac stereo profi covox |
| 20 | port 0f,4f dac stereo covox |
| 21 | port fb dac mono pentagon/atm (sd mode 2 off) |
| 22 | port b3 dac mono gs covox |
| 23 | port df dac mono specdrum, port 1f kempston alias |
| 24 | port bf3b,ff3b ula+ |
| 25 | port 0b z80 dma |
| 26 | port eff7 pentagon 1024 memory |
| 27 | port 183b,193b,1a3b,1b3b,1c3b,1d3b,1e3b,1f3b z80 ctc |
| 31 | register reset mode (soft or hard reset selection) |
0x89,0x88,0x87,0x86 (137-134) => Expansion Bus Decoding Enables (0x89 is MSB) (soft reset if bit 31 = 0, hard reset if bit 31 = 1 : all 1)
----- ----- ----- ... ----- The internal port decoding enables always apply. When the expansion bus is on, the expansion port decoding enables are logically ANDed with the internal enables. A zero bit indicates the internal device is disabled. If the expansion bus is on, this allows io cycles for disabled ports to propagate to the expansion bus, otherwise corresponding io cycles to the expansion bus are filtered.
| Bits | Description |
|---|---|
| 7:6 | Reserved, must be 0 |
| 5 | Propagate port 0xeff7 io cycles (hard reset = 0) |
| 4 | Propagate port 0xff io cycles (hard reset = 0) |
| 3 | Propagate port 0x1ffd io cycles (hard reset = 0) |
| 2 | Propagate port 0xdffd io cycles (hard reset = 0) |
| 1 | Propagate port 0x7ffd io cycles (hard reset = 0) |
| 0 | Propagate port 0xfe io cycles (hard reset = 0) |
If any of the bits are set, io cycles for the corresponding ports are propagated to the expansion bus when the expansion bus is on. If the internal port decode is still active, any response sent by devices on the expansion bus will be ignored. The purpose here is to allow external peripherals to monitor changes in state inside the zx next. Port 0xfe is treated specially so that external keyboards can be attached. When its propagate bit is set, the value read from the bus will be mixed into keyboard reads on port 0xfe.
| Bits | Description |
|---|---|
| 7 | 1 to enable alt rom |
| 6 | 1 to make alt rom visible only during writes, otherwise replaces rom during reads |
| 5 | 1 to lock ROM1 (48K rom) |
| 4 | 1 to lock ROM0 (128K rom) |
| 3 | 1 to enable alt rom |
| 2 | 1 to make alt rom visible only during writes, otherwise replaces rom during reads |
| 1 | 1 to lock ROM1 (48K rom) |
| 0 | 1 to lock ROM0 (128K rom) |
IMMEDIATE AFTER SOFT RESET (copied into bits 7-4) The locking mechanism also applies if the alt rom is not enabled. For the +3 and zx next, if the two lock bits are not zero, then the corresponding rom page is locked in place. Other models use the bits to preferentially lock the corresponding 48K rom or the 128K rom.
| Bits | Description |
|---|---|
| 7 | port 0xdffd bit 0 \ RAM |
| 6:4 | port 0x7ffd bits 2:0 / bank 0-15 |
| 2 | port 0x1ffd bit 0 paging mode |
| 1 | port 0x1ffd bit 2 \ ROM |
| 0 | port 0x7ffd bit 4 / select |
| 1 | port 0x1ffd bit 2 \ all |
| 0 | port 0x1ffd bit 1 / RAM |
R bit 3 = 1 W bit 3 = 1 to change RAM bank, 0 = no change to mmu6 / mmu7 / RAM bank in ports 0x7ffd, 0xdffd If bit 2 = paging mode = 0 (normal) If bit 2 = paging mode = 1 (special allRAM) Writes can affect all ports 0x7ffd, 0xdffd, 0x1ffd Writes always change the ROM / allRAM mapping Writes immediately change the current mmu mapping as if by port write
| Bits | Description |
|---|---|
| 7:2 | Reserved, must be zero |
| 1:0 | Mapping mode applied 00 = Standard ZX 128k +3 01 = Reserved 10 = Pentagon 512K 11 = Pentagon 1024K (limited to 768K on 1MB machines) |
* Standard ZX 128K +3 = principally ports 0x7ffd, 0xdffd, 0x1ffd
* Pentagon 512K = principally port 0x7ffd
* Pentagon 1024K = principally ports 0x7ffd, 0xeff7
** The mapping modes affect how ports 0x7ffd, 0xdffd, 0x1ffd and 0xeff7 carry out memory paging, see ports.txt
| Bits | Description |
|---|---|
| 7:6 | Reserved, must be 0 |
| 5 | Enable UART on GPIO 14,15 (overrides gpio)* (soft reset = 0) |
| 4 | 0 to connect Rx to GPIO 15, Tx to GPIO 14 (for comm with pi hats) (soft reset = 0) = 1 to connect Rx to GPIO 14, Tx to GPIO 15 (for comm with pi) |
| 3 | Enable I2C on GPIO 2,3 (override gpio) (soft reset = 0) |
| 2:1 | Reserved, must be 0 |
| 0 | Enable SPI on GPIO 7,8,9,10,11 (overrides gpio) (soft reset = 0) |
* GPIO 16,17 will function as rtr_n and cts_n if the uart is in hw flow control mode
| Bits | Description |
|---|---|
| 7:6 | I2S enable (soft reset = 00) 00 = i2s off 01 = i2s is mono source right 10 = i2s is mono source left 11 = i2s is stereo |
| 5 | Reserved, must be 0 |
| 4 | 0 PCM_DOUT to pi, PCM_DIN from pi (hats) (soft reset = 0) = 1 PCM_DOUT from pi, PCM_DIN to pi (pi) |
| 3 | Mute left side (soft reset = 0) |
| 2 | Mute right side (soft reset = 0) |
| 1 | Reserved must be 1 |
| 0 | Direct i2s audio to EAR on port 0xFE (soft reset = 0) |
| Bits | Description |
|---|---|
| 7 | 1 to enable automap on address 0x0038 (instruction fetch) |
| 6 | 1 to enable automap on address 0x0030 (instruction fetch) |
| 5 | 1 to enable automap on address 0x0028 (instruction fetch) |
| 4 | 1 to enable automap on address 0x0020 (instruction fetch) |
| 3 | 1 to enable automap on address 0x0018 (instruction fetch) |
| 2 | 1 to enable automap on address 0x0010 (instruction fetch) |
| 1 | 1 to enable automap on address 0x0008 (instruction fetch) |
| 0 | 1 to enable automap on address 0x0000 (instruction fetch) |
| Bits | Description |
|---|---|
| 7 | 1 for always else only when rom3 is present (0x0038) |
| 6 | 1 for always else only when rom3 is present (0x0030) |
| 5 | 1 for always else only when rom3 is present (0x0028) |
| 4 | 1 for always else only when rom3 is present (0x0020) |
| 3 | 1 for always else only when rom3 is present (0x0018) |
| 2 | 1 for always else only when rom3 is present (0x0010) |
| 1 | 1 for always else only when rom3 is present (0x0008) |
| 0 | 1 for always else only when rom3 is present (0x0000) |
| Bits | Description |
|---|---|
| 7 | 1 for instant mapping else delayed (0x0038) |
| 6 | 1 for instant mapping else delayed (0x0030) |
| 5 | 1 for instant mapping else delayed (0x0028) |
| 4 | 1 for instant mapping else delayed (0x0020) |
| 3 | 1 for instant mapping else delayed (0x0018) |
| 2 | 1 for instant mapping else delayed (0x0010) |
| 1 | 1 for instant mapping else delayed (0x0008) |
| 0 | 1 for instant mapping else delayed (0x0000) |
| Bits | Description |
|---|---|
| 7 | 1 to enable automap on addresses 0x3DXX (instruction fetch, instant, ROM3) > TRDOS |
| 6 | 1 to disable automap on addresses 0x1FF8-0x1FFF (instruction fetch, delayed) |
| 5 | 1 to enable automap on address 0x056A (instruction fetch, delayed, ROM3) \ tape traps |
| 4 | 1 to enable automap on address 0x04D7 (instruction fetch, delayed, ROM3) / nextzxos (better compatibility) |
| 3 | 1 to enable automap on address 0x0562 (instruction fetch, delayed, ROM3) \ tape traps |
| 2 | 1 to enable automap on address 0x04C6 (instruction fetch, delayed, ROM3) / esxdos + original divmmc |
| 1 | 1 to enable automap on address 0x0066 (instruction fetch + button, instant) |
| 0 | 1 to enable automap on address 0x0066 (instruction fetch + button, delayed) |
| Bits | Description |
|---|---|
| 7:5 | Programmable portion of im2 vector* |
| 4 | Reserved must be 0 |
| 3 | Enable stackless nmi response** |
| 2:1 | Current Z80 interrupt mode 0,1,2 (read only, write ignored) |
| 0 | Maskable interrupt mode: pulse (0) or hw im2 mode (1) |
| 7:5 | nextreg 0xC0 bits 7:5 |
| 4:1 | 0 line interrupt (highest priority) = 1 uart0 Rx = 2 uart1 Rx = 3-10 ctc channels 0-7 = 11 ula = 12 uart0 Tx = 13 uart1 Tx (lowest priority) |
| 0 | 0 |
* In hw im2 mode the interrupt vector generated is:
* In hw im2 mode the expansion bus is the lowest priority interrupter and if no vector is supplied externally then 0xFF is generated.
** The return address pushed during an nmi acknowledge cycle will be written to nextreg instead of memory (the stack pointer will be decremented) and the first RETN after the acknowledge will take its return address from nextreg instead of memory (the stack pointer will be incremented). If bit 3 = 0 and in other circumstances, RETN functions normally.
| Bits | Description |
|---|---|
| 7 | Reserved must be zero |
| 6 | UART1 Tx empty |
| 5 | UART1 Rx near full \ shared |
| 4 | UART1 Rx available / interrupt |
| 3 | Reserved must be zero |
| 2 | UART0 Tx empty |
| 1 | UART0 Rx near full \ shared |
| 0 | UART0 Rx available / interrupt |
* Rx near full overrides Rx available
* If a device interrupt is disabled, it enters a polled mode
| Bits | Description |
|---|---|
| 7:2 | Reserved must be 0 |
| 1 | Line |
| 0 | ULA |
* (R) Set bits indicate the device generated an interrupt in the past or an interrupt is pending
* (W) Set bits clear the status. In hw im2 mode the status will continue to read as set until the interrupt pending condition is cleared
| Bits | Description |
|---|---|
| 7 | ctc channel 7 zc/to |
| 6 | ctc channel 6 zc/to |
| 5 | ctc channel 5 zc/to |
| 4 | ctc channel 4 zc/to |
| 3 | ctc channel 3 zc/to |
| 2 | ctc channel 2 zc/to |
| 1 | ctc channel 1 zc/to |
| 0 | ctc channel 0 zc/to |
* (R) Set bits indicate the device generated an interrupt in the past or an interrupt is pending
* (W) Set bits clear the status. In hw im2 mode the status will continue to read as set until the interrupt pending condition is cleared
| Bits | Description |
|---|---|
| 7 | Reserved must be zero |
| 6 | UART1 Tx empty |
| 5 | UART1 Rx half full \ shared |
| 4 | UART1 Rx available / interrupt |
| 3 | Reserved must be zero |
| 2 | UART0 Tx empty |
| 1 | UART0 Rx half full \ shared |
| 0 | UART0 Rx available / interrupt |
* (R) Set bits indicate the device generated an interrupt in the past or an interrupt is pending
* (W) Set bits clear the status. In hw im2 mode the status will continue to read as set until the interrupt pending condition is cleared
| Bits | Description |
|---|---|
| 7 | Reserved must be zero |
| 6 | UART1 Tx empty |
| 5 | UART1 Rx half full \ shared |
| 4 | UART1 Rx available / interrupt |
| 3 | Reserved must be zero |
| 2 | UART0 Tx empty |
| 1 | UART0 Rx half full \ shared |
| 0 | UART0 Rx available / interrupt |
* Set bits indicate the corresponding interrupt will interrupt a dma operation when in hw im2 mode
| Bits | Description |
|---|---|
| 7 | 1 if in select mode |
| 1:0 | indicate currently selected device |
| Bits | Description |
|---|---|
| 7 | 1 to enter select mode, 0 to enter selected device mode (no other bits have effect)*** |
| 6 | 1 to change selected device** |
| 1:0 | selected device |
| Bits | Description |
|---|---|
| 0 | dna bit (serial stream shifts left) |
| Bits | Description |
|---|---|
| 7 | 1 to enter select mode (write has no other effect)* |
| Bits | Description |
|---|---|
| 6 | 1 if XADC is busy with conversion (BUSY) |
| 1 | 1 if XADC conversion completed since last read (EOC, read clears) |
| 0 | 1 if XADC conversion sequence completed since last read (EOS, read clears) |
| Bits | Description |
|---|---|
| 7 | 1 to enter select mode (write has no other effect)* |
| 6 | 1 to reset XADC (RESET) |
| 0 | 1 to start conversion (CONVST) |
* Re-enter select mode at any time by writing to the register with bit 7 set
** Select a device to communicate with by writing to the register with bits 6 & 7 set
*** Exit select mode by writing zero to bit 7; thereafter the particular device is attached to the nextreg
| Bits | Description |
|---|---|
| 7 | 1 to write to XADC DRP port, 0 to read from XADC DRP port** |
| 6:0 | XADC DRP register address DADDR |
* An XADC register read or write is/ initiated by writing to this register
* There must be at least six 28 MHz cycles after each r/w to this register
** Reads as 0