| Bits | Description |
|---|
| 7 | ctc channel 7 zc/to |
| 6 | ctc channel 6 zc/to |
| 5 | ctc channel 5 zc/to |
| 4 | ctc channel 4 zc/to |
| 3 | ctc channel 3 zc/to |
| 2 | ctc channel 2 zc/to |
| 1 | ctc channel 1 zc/to |
| 0 | ctc channel 0 zc/to |
Set bits indicate the corresponding interrupt will interrupt a dma operation when in hw im2 mode