| Bits | Description |
|---|---|
| 7 | Reserved must be zero |
| 6 | UART1 Tx empty |
| 5 | UART1 Rx half full \ shared |
| 4 | UART1 Rx available / interrupt |
| 3 | Reserved must be zero |
| 2 | UART0 Tx empty |
| 1 | UART0 Rx half full \ shared |
| 0 | UART0 Rx available / interrupt |
* (R) Set bits indicate the device generated an interrupt in the past or an interrupt is pending
* (W) Set bits clear the status. In hw im2 mode the status will continue to read as set until the interrupt pending condition is cleared