| Bits | Description |
|---|
| 0 | port bf3b,ff3b ula+ |
| 1 | port 0b z80 dma |
| 2 | port eff7 pentagon 1024 memory |
| 3 | port 183b,193b,1a3b,1b3b,1c3b,1d3b,1e3b,1f3b z80 ctc |
| 7 | register reset mode (soft or hard reset selection) |
Notes:
The internal port decoding enables always apply.
When the expansion bus is on, the expansion port decoding enables are logically ANDed with the internal enables.
A zero bit indicates the internal device is disabled. If the expansion bus is on, this allows io cycles for
disabled ports to propagate to the expansion bus, otherwise corresponding io cycles to the expansion bus are filtered.