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Group NameRW76543210DescriptionHD
When NR09:D4 is set■■ •••••••Sprite number¹ / Pattern Number²
• Pattern Address Offset³

The above applies only when the sprites port is in Lockstep and effectively performs an OUT to port 12347 (303Bh) with the same value otherwise the section below applies

When NR09:D4 is NOT set■■ 0•••••••Sprite number¹

1 Values are 0 to 127
2 Values are 0 to 63
3 Adds 128 to pattern address
This register selects which sprite has its attributes connected to the registers that follow:
NextREG 53 (36h) – NextREG 57 (39h) and their auto-incremented counterparts
NextREG 117 (75h) – NextREG 121 (79h)

NextREG 53 (35h) – Sprite Attribute 0

Group NameRWData BitsDescriptionHD
76543210
X Coordinate LSB■••••••••Sprite X Coordinate LSB

MSB is in NextREG 55 (37h):D0

NextREG 54 (36h) – Sprite Attribute 1

Group NameRWData BitsDescriptionHD
76543210
Y Coordinate LSB■••••••••Sprite Y Coordinate LSB

MSB is in NextREG 57 (39h):D0

NextREG 55 (37h) – Sprite Attribute 2

Group NameRWData BitsDescriptionHD
76543210
Sprite Attribute 2■eeeedcbaSee notes

a For relative sprites: Indicates that e is relative to the anchor's palette offset
For normal sprites: Sprite's X Coordinate MSB (See NextREG 53 (35h) for LSB)
b 90° Clockwise Rotation Control (0 = No, 1 = Yes)
c Vertical Mirror Control (0 = No, 1 = Yes)
d Horizontal Mirror Control (0 = No, 1 = Yes)
e 4-bit palette offset
Rotation is applied before mirroring

NextREG 56 (38h) – Sprite Attribute 3

Group NameRWData BitsDescriptionHD
76543210
Sprite Attribute 3■cbaaaaaaSee notes

a Sprite pattern to use. Possible values = 0 to 63
b Attribute 4 switch (0 = No, 1 = Yes)
If b = 0 then the sprite is fully described by Attributes 0 to 3. The sprite pattern is an 8-bit one identified by pattern a and is an anchor and cannot be made relative. Sprite display behaves as if Attribute 4 = 0
If b = 1 then the sprite is further described by Attribute 4 that follows in NextREG 57 (39h)
c Visibility Control (0 = Invisible, 1 = Visible)

NextREG 57 (39h) – Sprite Attribute 4

Group NameRWData BitsDescriptionHD
76543210
Sprite Attribute 4■fedccbbaSee notes

a For relative sprites: Indicates that the sprite pattern number is relative to the anchor's
For normal sprites: Sprite's Y Coordinate MSB (See NextREG 54 (36h) for LSB)
b For normal and relative, composite type sprites indicates X direction Magnification:
(00 = 1x, 01 = 2x, 10 = 4x, 11 = 8x)
For relative, unified type sprites it's 0
c For normal and relative, composite type sprites indicates Y direction Magnification:
(00 = 1x, 01 = 2x, 10 = 4x, 11 = 8x)
For relative, unified type sprites it's 0
d For normal sprites, indicates that the attached relative sprites are: 0 for Composite, 1 for Unified
For relative sprites contains the 7th pattern bit if the sprite pattern is 4-bit.
e For normal sprites contains the 7th pattern bit if the sprite pattern is 4-bit.
For relative sprites it's 1.
f 4-bit pattern switch: 1 if the sprite pattern is 4-bit otherwise 0
{f,e} must not equal {0,1} as this combination is used to indicate a relative sprite. See notes above

NextREG 64 (40h) – Palette Index Select

Group NameRWData BitsDescriptionHD
76543210
Palette Index Select■■••••••••Palette index number

Selects the palette index to change the associated colour
For ULA only, INKs are mapped to indices 0 through 7, BRIGHT INKs to indices 8 through 15, PAPERs to indices 16 through 23 and BRIGHT PAPERs to indices 24 through 31
In EnhancedULA mode, INKs come from a subset of indices from 0 through 127 and PAPERs from a subset of indices from 128 through 255.
The number of active indices depends on the number of attribute bits assigned to INK and PAPER out of the attribute byte
In ULAplus mode, the last 64 entries (indices 192 to 255) hold the ULAplus palette
The ULA always takes border colour from PAPER for standard ULA and EnhancedULA

NextREG 65 (41h) – 8-bit Palette Data

Group NameRWData BitsDescriptionHD
76543210
8-bit Palette Entry■■••••••••Colour entry in RRRGGGBB format

The lower blue bit of the 9-bit internal colour will be the logical OR of Bits 0 and 1 of the 8-bit entry. After each write, the palette index is auto-incremented to the next index if the auto-increment has been enabled in NextREG 67 (43h):D7
Reads do not auto-increment the index. Any other bits associated with the index will be zeroed

NextREG 66 (42h) – EnhancedULA Attribute Byte Format

Group NameRWData BitsDescriptionHD
76543210
Attribute Byte Format■■••••••••Attrbute byte's INK representation mask*

* Soft reset defaults to 7
Not set bits, indicate PAPER. Acceptable values are made by setting each bit from 0 on, in sequence: (1,3,7,15,31,63,127 and 255) which effectively splits the attribute byte setting the INKs from the right side and the PAPERs from what's left. INKs are mapped from Index 0 onwards on the palette while PAPERs and BORDER are mapped from Index 128 onwards
A full value of 255 will set all colours to INK (Full INK mode) and PAPER and BORDER are taken from the fallback colour defined in NextREG 74 (4Ah)
If the mask is not one of those listed above, the INK is still the result of logically ANDing the mask with the attribute byte but the PAPER and BORDER will be taken from the fallback colour
Example:
00111011 will be ANDed with the attribute byte to form the INK index and PAPER will come from the fallback colour

NextREG 67 (43h) – Palette Control

Group NameRWData BitsDescriptionH[?]
76543210
EnhancedULA control■■ •Enable EnhancedULA[?]
Active ULA¹ Palette■■ 0 First Palette[?]
1 Second Palette
Active Layer 2 Palette■■ 0 First Palette[?]
1 Second Palette
Active Sprites Palette■■ 0 First Palette[?]
1 Second Palette
Palette Select for Read/Write■■ 000 Layers 0/1 (ULA) First[?]
100 Layers 0/1 (ULA) Second
001 Layer 2 First
101 Layer 2 Second
010 Sprites First
110 Sprites Second
011 Layer 3 (Tilemap) First
111 Layer 3 (Tilemap) Second
Palette Auto-increment Control■■• Disable Palette Write Auto-increment[?]

* After a soft reset defaults to 000
¹ ULA refers to all ULA modes (Layers 0 and 1)

NextREG 68 (44h) – 9-bit Palette Data

Group NameRWData BitsDescriptionH[?]
76543210
MSB Colour (1st Write) Non L2■••••••••MSB (RRRGGGBB) format – non L2 palette[?]
LSB Blue (2nd Write) Non L2■■ •LSB B format – non L2 palette
Reserved Non L2■ 0 0 0 0 0 0 0 Reserved, must be 0 – non L2 palette
MSB Colour (1st Write) L2■••••••••MSB (RRRGGGBB) format – L2 palette[?]
LSB Blue + Priority L2 (2nd W)■■• •L2 priority (D7) and LSB B(D0)[?]
Reserved L2■ 0 0 0 0 0 0 Reserved, must be 0 L2 palette[?]

9-bit Palette Data is entered in two consecutive writes; the second write auto-increments the palette index if auto-increment is enabled in NextREG 67 (43h):D7
If writing an L2 palette, the second write's D7 holds the L2 priority bit which if set (1) brings the colour defined at that index on top of all other layers. If you also need the same colour in regular priority (for example: for environmental masking) you will have to set it up again, this time with no priority
Reads return the second byte and do not auto-increment
Writes to NextREGs 64, 65 and 67 (40h, 41h and 43h) reset to the 1st write

NextREG 74 (4Ah) – Fallback Colour Value

Group NameRWData BitsDescriptionH[?]
76543210
Fallback Colour■■••••••••8-bit colour if all layers are transparent[?]

* Soft reset sets the default fallback to 227 (E3h) as it must be the same for when ULAplus programs hit the transparent colour, otherwise nothing will be displayed

NextREG 75 (4Bh) – Sprite Transparency Index

Group NameRWData BitsDescriptionH[?]
76543210
Transparency Index■■••••••••Sprite colour index treated as transparent[?]

* Soft reset defaults to 227 (E3h)
For 4-bit sprites, only 4-bits are used (from D0 to D3)
For example for 8-bit transparency index 227 (E3h) the 4-bit equivalent will be 03 (03h)

NextREG 76 (4Ch) – Layer 3 (Tilemap) Transparency Index

Group NameRWData BitsDescriptionH[?]
76543210
Transparency Index■■ ••••4-bit index treated as transparent[?]
Reserved■■ 0 0 0 0 Reserved, must be 0[?]

* Soft reset defaults to 15 (0Fh)

NextREG 80 (50h) – MMU Slot 0 Control

Group NameRWData BitsDescriptionH[?]
76543210
MMU Slot 0 Control■■••••••••8K RAM page for address 0000h–1FFFh[?]

* Default 255 (FFh)
Pages range from 0 to 223 on a fully expanded Next. A value of 255 (FFh) makes the ROM become visible

NextREG 81 (51h) – MMU Slot 1 Control

Group NameRWData BitsDescriptionH[?]
76543210
MMU Slot 1 Control■■••••••••8K RAM page for address 2000h–3FFFh[?]

* Default 255 (FFh)
Pages range from 0 to 223 on a fully expanded Next. A value of 255 (FFh) makes the ROM become visible

NextREG 82 (52h) – MMU Slot 2 Control

Group NameRWData BitsDescriptionH[?]
76543210
MMU Slot 2 Control■■••••••••8K RAM page for address 4000h–5FFFh[?]

* Default 10 (0Ah)
Pages range from 0 to 223 on a fully expanded Next

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ZX Spectrum Next User Manual, 3rd Edition (ISBN 978-1-5272-5496-1), written and illustrated by Phoebus R. Dokos. Copyright © 2020-2024 Phoebus Dokos / SpecNext Ltd. Licensed under CC BY-NC-SA 4.0. This is a transcription and can contain errors; check any doubt against the printed page.