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Chapter 22 – IN, OUT and the Next Registers

We can instruct the processor to read from and write to memory by using PEEK, POKE and their variants. For all the possibilities, examine Chapter 23 – The Memory. The processor itself does not really care whether memory is ROM, RAM or even nothing at all; it just knows that there are 65536 memory addresses, and it can read a byte from each one, even if it's nonsense, and write a byte to each one, even if it gets lost because the address is read-only. In a completely analogous way, there are also 65536 hardware addresses, called I/O ports (Input/Output ports) that are separate from memory. These are used by the processor for communicating with attached devices like the keyboard or the display, and they can be controlled from NextBASIC by using the IN function and the OUT statement. There's a number of I/O ports, specific to the ZX Spectrum Next which control its advanced functions; they too, are accessible with IN and OUT, but two of them, are also accessible via a special dual statement/function, called REG.

IN and OUT

IN is a function like the simplest form of PEEK:

IN port

It has one argument, the hardware address port, and its result is a byte read from that port. OUT on the other hand is a statement like a simple POKE:

OUT port, v

which writes value v to the hardware address port.

Hardware address decoding

How the address is interpreted depends on the hardware in the computer and attached devices. In previous versions of the ZX Spectrum line of computers and especially in legacy peripherals, many different port addresses mapped to the same device. This is called partial decoding and happened because some address bits were ignored in the hardware to save on cost. As a consequence, entire ranges of port addresses were reserved by individual peripherals. This made it hard for new peripherals to find non-conflicting ports to use and, in reality, many did not and only managed to use ports that didn't conflict with the most popular peripherals. The situation was somewhat mitigated by the fact that only a couple of peripherals could be connected to the older ZX Spectrum machines at once, due to electrical limitations. Today, where modern ZX Spectrum implementations pack many devices into their hardware, this port conflict problem returns with renewed urgency, as any pair of devices with conflicting port addresses are not compatible with each other.

The ZX Spectrum Next fully decodes port addresses for new peripherals (meaning it does not ignore any address line), but because a lot of the hardware it contains is based on existing devices, those must continue to be partially decoded. In order to best understand the issues at hand, and in the table that follows which contains all available port addresses on the ZX Spectrum Next, it is best if we approach them as written in binary. That way we can easily show which bits are being ignored by a specific peripheral. Each hardware address is 16 bits wide, which we shall call (using A for address):

A15A14A13A12A11A10A9A8A7A6A5A4A3A2A1A0

Here A0 is the 1st bit, A1 the 2nd bit, A2 the 3rd bit, A3 the 4th bit and so on. The table that follows shows which bits are important for the corresponding device. For example, the ULA only needs A0 to be 0 in order to respond, which means it will respond to all 32768 even port addresses and not just its official port 254 (FEh). The byte read or written has 8 bits, and these are often referred to (using D for data) as:

D7D6D5D4D3D2D1D0
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Here is a list of the port addresses used with their decoding. For the reason mentioned, only the ULA has an even port address and every even-numbered port IN will result in the ULA being read.

R W A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Port (Hex) Description
■ ■ 0 FEh ULA
■ ■ 1 1 1 1 1 1 1 1 FFh Timex video, Floating bus
■ 0 0 1 7FFDh Memory Paging Control
■ 0 1 0 1 7FFDh Memory Paging Control (+3/Next only)
■ 1 1 0 1 0 1 DFFDh Next Memory Bank Select1
■ 0 0 0 1 0 1 1FFDh +3 Memory Paging Control
■ 0 0 1 0 0 1 2FFDh +3 FDC Status
■ ■ 0 0 1 1 0 1 3FFDh +3 FDC Control
■ 1 1 1 0 1 1 1 1 0 1 1 1 EFF7h Pentagon 1024K Memory Paging Cntl.
■ 0 0 0 0 0 1 +3 Floating bus
■ ■ 0 0 1 0 0 1 0 0 0 0 1 1 1 0 1 1 243Bh NextREG Select
■ ■ 0 0 1 0 0 1 0 1 0 0 1 1 1 0 1 1 253Bh NextREG Data
■ ■ 0 0 0 1 0 0 0 0 0 0 1 1 1 0 1 1 103Bh I²C SCL
■ ■ 0 0 0 1 0 0 0 1 0 0 1 1 1 0 1 1 113Bh I²C SDA
■ ■ 0 0 0 1 0 0 1 0 0 0 1 1 1 0 1 1 123Bh Layer 2
■ ■ 0 0 0 1 0 0 1 1 0 0 1 1 1 0 1 1 133Bh UART Tx
■ ■ 0 0 0 1 0 1 0 0 0 0 1 1 1 0 1 1 143Bh UART Rx
■ ■ 0 0 0 1 0 1 0 1 0 0 1 1 1 0 1 1 153Bh UART Select
■ ■ 0 0 0 1 0 1 1 0 0 0 1 1 1 0 1 1 163Bh UART Frame
■ ■ 0 0 0 1 1 0 0 1 1 1 0 1 1 183Bh CTC Channel 02
■ ■ 0 0 0 1 1 0 0 1 1 1 0 1 1 193Bh CTC Channel 12
■ ■ 0 0 0 1 1 0 0 1 1 1 0 1 1 1A3Bh CTC Channel 22
■ ■ 0 0 0 1 1 0 0 1 1 1 0 1 1 1B3Bh CTC Channel 32
■ ■ 0 0 0 1 1 0 0 1 1 1 0 1 1 1C3Bh CTC Channel 42
■ ■ 0 0 0 1 1 0 0 1 1 1 0 1 1 1D3Bh CTC Channel 52
■ ■ 0 0 0 1 1 0 0 1 1 1 0 1 1 1E3Bh CTC Channel 62
■ ■ 0 0 0 1 1 0 0 1 1 1 0 1 1 1F3Bh CTC Channel 72
■ 1 0 1 1 1 1 1 1 0 0 1 1 1 0 1 1 BF3Bh ULAplus Register
■ ■ 1 1 1 1 1 1 1 1 0 0 1 1 1 0 1 1 FF3Bh ULAplus Data
■ ■ 0 0 0 0 1 0 1 1 0Bh z80DMA3
■ ■ 0 1 1 0 1 0 1 1 6Bh zxnDMA3
■ ■ 1 1 1 0 1 FFFDh AY Register
■ ■ 1 0 1 0 1 BFFDh AY Data (readable on +3/Next only)
■ 1 0 0 1 0 1 BFF5h AY Inf (inside BFFDh decoding)
■ 0 0 0 1 1 1 1 1 1Fh DAC A
■ 1 1 1 1 0 0 0 1 F1h DAC A4
■ 0 0 1 1 1 1 1 1 3Fh DAC A
■ 0 0 0 0 1 1 1 1 0Fh DAC B
■ 1 1 1 1 0 0 1 1 F3h DAC B
■ 1 1 0 1 1 1 1 1 DFh DAC A,D
■ 1 1 1 1 1 0 1 1 FBh DAC A,D
■ 1 0 1 1 0 0 1 1 B3h DAC B,C
■ 0 1 0 0 1 1 1 1 4Fh DAC C
■ 1 1 1 1 1 0 0 1 F9h DAC C4
■ 0 1 0 1 1 1 1 1 5Fh DAC D
■ 1 1 1 0 0 1 1 1 E7h SPI CS (SD card, Flash, RPi0)
■ ■ 1 1 1 0 1 0 1 1 EBh SPI DATA
■ ■ 1 1 1 0 0 0 1 1 E3h divMMC control

1 Precedence over AY 2: Temporarily reduced to first four CTC channels only 3: Selecting either DMA port, also selects the mode in which the DMA operates 4: Precedence over xxFD

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R W A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Port (Hex) Description
■ 1 0 1 1 1 1 0 1 1 1 1 1 FBDFh KEMPSTON Mouse X
■ 1 1 1 1 1 1 0 1 1 1 1 1 FFDFh KEMPSTON Mouse Y
■ 1 0 1 0 1 1 0 1 1 1 1 1 FADFh KEMPSTON Mouse Wheel, Buttons
■ 0 0 0 1 1 1 1 1 1Fh KEMPSTON Joystick 1
■ 1 1 0 1 1 1 1 1 DFh KEMPSTON Joystick 1 Alias
■ 0 0 1 1 0 1 1 1 37h KEMPSTON Joystick 2
■ ■ 0 0 0 1 1 1 1 1 1Fh Multiface 1 Disable
■ ■ 1 0 0 1 1 1 1 1 9Fh Multiface 1 Enable
■ ■ 0 0 0 1 1 1 1 1 1Fh Multiface 128 v87.12 Disable
■ ■ 1 0 0 1 1 1 1 1 9Fh Multiface 128 v87.12 Enable
■ ■ 0 0 1 1 1 1 1 1 3Fh Multiface 128 v87.2 Disable
■ ■ 1 0 1 1 1 1 1 1 BFh Multiface 128 v87.2 Enable
■ ■ 1 0 1 1 1 1 1 1 BFh Multiface +3 Disable
■ ■ 0 0 1 1 1 1 1 1 3Fh Multiface +3 Enable
■ ■ 0 0 1 1 0 0 0 0 0 0 1 1 1 0 1 1 303Bh Sprite slot flags
■ 0 1 0 1 0 1 1 1 57h Sprite Attributes
■ 0 1 0 1 1 0 1 1 5Bh Sprite Pattern

The above table describes the ports that are used to control and communicate with additional hardware features of the ZX Spectrum Next. Therein exist 17 ports that are of special signifance as they are unique to the ZX Spectrum Next. These are:

Port Name Address (Hex) Address (Dec) Description
NextReg Select 243Bh 9275 Communicates with the ZX Spectrum Next hardware
NextReg Data 253Bh 9531 Used after register selection to send and read data
I²C SCL 103Bh 4155 Used for I²C device communication (RTC etc)
I²C SDA 113Bh 4411 Sends/Receives data from/to the I²C bus
Layer 2 123Bh 4667 Used to control Layer 2
UART Tx 133Bh 4923 Transmits data from the UART
UART Rx 143Bh 5179 Receives data from the UART
UART Select 153Bh 5435 Selects which UART is in use
UART Frame 163Bh 5691 Sets up the UART framing
CTC 183Bh - 1FB3h 6203 - 8115 Configures the Counter Timer Circuits
z80DMA 0Bh 11 Programs the DMA in a z80DMA compatible mode
zxnDMA 6Bh 107 Programs the DMA in zxnDMA mode
SPI Select E7h 231 Selects an SPI peripheral (SD Card/Flash ROM/RPi0)
SPI DATA EBh 235 Sends/Receives Data via the SPI bus a byte at a time
SPRITE 303Bh 12347 Controls the Next Sprite Engine
SPRITE ATTR 57h 87 Sends Sprite Attributes to the Sprite Engine
SPRITE PATTERN 5Bh 91 Sends Sprite Pattern to the Sprite Engine
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Two of the most important ports in this list are collectively called Next Register or NextREG for short. Most of the machine's features can be controlled through NextREG.

Accessing the ZX Spectrum Next features with NextREG

We use a NextREG by first selecting it with the control port and then writing to – or reading from – the NextREG data port.

In NextBASIC this is achieved with two consecutive OUT commands in the case of writing or with a combination of consecutive OUT and IN in the case of reading from a NextREG.

The first command is directed to the Select port 9275 (243Bh), selecting a specific register and the second to the Data port 9531 (253Bh) to modify or read the value stored there.

If given from NextBASIC, these commands must be given consecutively in one line as NextBASIC may do something different with NextREG in-between commands. If you give the first and then wait to give the second, NextBASIC may have changed the Select register in the meantime; so by giving them together you give it no time to do something else.

The Z80N CPU which powers the ZX Spectrum Next, also provides a special NEXTREG instruction and this is referenced in Appendix A.

Finally, as mentioned in the introduction, in order to read NextREG, NextBASIC also has a specialised command and function called REG, which is much easier to use than the combination of OUT and IN keywords.

We'll showcase both methods here, in order for you to be able to use either as there are cases where the ZX Spectrum Next's facilities are still available but without NextBASIC to provide access to them. The command as a statement has the form:

REG n,v

which is essentially the same as doing:

OUT 9275, n:OUT 9531, v

Obviously n is the register number and v is the value we modify the register with. As a function, REG has the following form:

% REG n or REG n

as it works with both the integer as well as the standard expression evaluators. This essentially is the same as executing

OUT 9275, n: %x = % IN 9531 (or the equivalent x = IN 9531).

Let's give one simple example in both forms and let's mix-and-match a bit as well, to show the equivalency:

Assuming we want to change speeds to 28MHz, we could give:

RUN AT 3

or

OUT 9275, 7:OUT 9531, 3

and we can verify that it is set by either bringing up any NextBASIC menu (menus list the currently set speed on top) with the EDIT key or by doing:

OUT 9275,7: PRINT % IN 9531 & @11

Which is the same as

PRINT % REG 7&@11
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You can verify this actually changes things by doing a RUN AT 2 and give the OUT/IN sequence again. As you will see from the list that follows, not every NextREG is dedicated solely to one function; in this case the only bits that concerned us were Bits 0 and 1 and that's why we used a 2-bit bitmask with the bitwise AND operator &. For the same example using just the REG command, our line would have been as simple as:

REG 7,3

In our example in Chapter 17 where we read NextREG 5h we also used bit shifting which is a great way to get the value of a single bit in a register. In our case we only needed bit 2 of the register so after getting the specific bit by bitwise AND (&) the register value with a 3-bit bitmask, we shifted it two places (bits) to the right by using the right bit-shifting operator (>>). That way we were able to get the value of the single register bit.

Generally speaking, you will often want to modify individual bits in a NextREG without changing the remaining ones.

You can do this by first reading the NextREG and then masking off the bits you want to leave unchanged by using bitwise AND (&) and finally write that value with the new bits added in.

We'll list all of NextREGs below in numerical order. Not every register is accessible, so pay attention to the key at the start of the list to understand whether a register can be read, written or both.

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Next Register Diagrams' Key

Symbol Meaning
Reserved value in either R(ead) or W(rite) condition but used in the inverse – Not Applicable
Reserved value - Not Applicable
X Reserved value MUST be X
Not Applicable / Don't care
R Read (if marked). Unmarked means Not Applicable
W Write (if marked). Unmarked means Not Applicable
H Hard Reset / Soft Reset / Config Mode. Unmarked means Soft Reset if there's a value in column D
D Contains the default value after a reset (Soft, Hard or Config as marked in column H).* refers to notes below
■ In columns R/W marks the status of the register. In column H means Hard Reset
♦ Means Config Mode
• Means any value (0 or 1)
N Any letter in a data bit position refers you to the notes below

NextREG 00 (00h) – Machine ID

Group NameRWData BitsDescriptionHD
76543210
Machine ID■00001000EMULATORS
00001010ZX Spectrum Next
11111010ZX Spectrum Next Anti-Brick
10011010Next Core on UnAmiga Reloaded
10101010Next Core on UnAmiga
10111010Next Core on SiDi
11001010Next Core on MiST
11011010Next Core on MiSTer
11101010Next Core on ZX-DOS/gomaDOS

NextREG 01 (01h) – Core Version

Group NameRWData BitsDescriptionHD
76543210
Minor Version Number■ ••••Minor Version
Major Version Number■•••• Major Version

See NextREG 14 (0Eh) for sub minor version number

NextREG 02 (02h) – Reset

Group NameRWData BitsDescriptionHD
76543210
Last System Reset Type■ 01Soft Reset
10Hard Reset
divMMC NMI source■ 0 divMMC NMI not generated by NR 02h
1 divMMC NMI generated by NR 02h
MF NMI source■ 0 MF NMI not generated by NR 02h
1 MF NMI generated by NR 02h
0 MF NMI not generated by I/O Trap²,*
1 MF NMI generated by I/O Trap²,*
Reserved■ Reserved
ESP/Expansion Bus R̅E̅S̅E̅T̅ flag■0 R̅E̅S̅E̅T̅ not asserted■0
1 R̅E̅S̅E̅T̅ asserted
Generate System Reset■ 01Generate Soft Reset
10Generate Hard Reset (reboot)
divMMC NMI control■ • Generate/Clear divMMC NMI³
MF NMI control■ • Generate/Clear MF NMI³
• If 0 Clear MF I/O Trap²,³
Reserved■ 0 0 Reserved (must be 0)
Generate ESP/Exp. Bus Reset¹■• Generate/Release Reset (Exp. Bus & ESP)

1 A full reset cycle for the ESP and Expansion Bus, requires setting D7 first to 1 for at least 100 ms and then to 0. The 100 ms assertion is required by the ESP module. If not explicitly released the Expansion Bus and ESP will stay with R̅E̅S̅E̅T̅ asserted until the next system hard reset
Of D0 – D1 Hard Reset has precedence
² Experimental
³ These signals are ignored if the Multiface, divMMC, DMA or external NMI master is active. Copper cannot clear these bits. Note: An I/O trap could occur at the same time as MF / divMMC cause; always check this bit in NMI ISR if important
* See NextREG 218 (DAh)

NextREG 03 (03h) – Machine Type

Group NameRWData BitsDescriptionHD
76543210
Machine Type■■ 000Configuration mode♦
001ZX 48K
010ZX 128K / +2
011ZX +2A / +2B / +3 / Next
100Pentagon Clones*
Display Timing user lock control■ 0 No User Lock on display timing applied
1 User lock on display timing applied
■ • Toggle User Lock on Display Timing■0
Display Timing■■ 000 Internal Use
001 ZX 48K
010 ZX 128K / +2
011 ZX +2A / +2B / +3 / Next
100 Pentagon*
NR 68 (44h) 2nd Byte Indicator■• Palette Entry (NR 68) Second Byte flag0
Display Timing change enable■• Allow changes to D4:60

* Pentagon timing is 50 Hz only
Machine type determines which ROMs are loaded and Display Timing also affects port decoding

[?]

Group NameRWData BitsDescriptionHD
76543210
16K RAM bank mapping■ •••••••Maps a 16K RAM Bank no. (0-127)*♦0
Reserved■ 0 Reserved, must be 0

* Maps a 16K RAM bank over the bottom 16K. Applies only in configuration mode when the boot rom is disabled
Even multiples of 256K are unreliable if storing data in RAM for the Next Core started

NextREG 05 (05h) – Peripheral 1 Settings

Group NameRWData BitsDescriptionHD
76543210
Scandoubler¹■■ 0Scandoubler Disabled
1Scandoubler Enabled
Vertical Frequency■■ 0 50 Hz mode
1 60 Hz mode*
Joystick 1**■■00 0 Sinclair 2 (12345)
00 1 Kempston 2 (Port 37h)
01 0 Kempston 1 (Port 1Fh)
01 1 MD 1 (Port 1Fh)
10 0 Cursor (56780)
10 1 MD 2 (Port 37h)
11 0 Sinclair 1 (67890)
11 1 User Defined Keys Joystick
Joystick 2**■■ 00 0 Sinclair 2 (12345)
00 1 Kempston 2 (Port 37h)
01 0 Kempston 1 (Port 1Fh)
01 1 MD 1 (Port 1Fh)
10 0 Cursor (56780)
10 1 MD 2 (Port 37h)
11 0 Sinclair 1 (67890)
11 1 User Defined Keys Joystick

¹ Enabled for VGA / HDMI, Disabled for RGB mode
* Pentagon Clones have no 60 Hz mode; when in Pentagon mode, every setting is 50 Hz.
** Joystick ports can be placed into I/O mode via NextREG 11 (Bh)
Programming the user defined keys joystick is done through the PS/2 keymap interface on NextREG 40 (28h), 41 (29h) and 43 (2Bh):

  1. Write 128 to NextREG 40 (28h)
  2. Write 0 (Left joystick) or 16 (Right joystick) to NextREG 41 (29h)
  3. Write 12 bytes to NextREG 43 (2Bh) in order. The bytes correspond to the twelve buttons on an MD pad as follows (Byte 0 to Byte 11):
    R, L, D, U, B, C, A, START, Y, Z, X, MODE
  4. Each byte written identifies a key in the 8x7 membrane; D5:3 select the row and D2:0 the column with 111 meaning no action

In Kempston and MD modes. excess buttons on an controller not read via ports will generate key input if so programmed

NextREG 06 (06h) – Peripheral 2 Settings

Group NameRWData BitsDescriptionHD
76543210
PSG Mode Control■■ 00YM
01AY
11Hold all PSGs in Reset
PS/2 Mode Control■■ 0 Keyboard Primary♦0
1 Mouse Primary
NMI Button Control■■ • NMI button enable*■0
divMMC NMI Control■■ • divMMC NMI** button enable■0
F3 Hotkey Control■■ • 50 Hz / 60 Hz hotkey enable1
Internal Speaker BEEP Control■■ 0 All audio copied to speaker■0
1 Only BEEP sounds diverted to speaker
F5, F6 and F8 Hotkey Control■■• CPU Speed and Exp. Bus hotkeys enable1

* NMI button refers to the button to the right side of the SD Card reader
** Refers to the Drive button to the left side of the SD Card reader

NextREG 07 (07h) – CPU Speed

Group NameRWData BitsDescriptionHD
76543210
CPU Speed Control¹■■ 003.5 MHz*
017 MHz
1014 MHz
1128 MHz
Reserved■ 0 0 0 0 0 0 Reserved, must be 0
Reserved■ 0 0 0 0 Reserved, must be 0
Current Actual² CPU Speed■ 00 3.5 MHz
01 7 MHz
10 14 MHz
11 28 MHz

* Soft reset defaults this to 00
¹ When read returns the Programmed CPU speed as it may differ from actual speed. See below
² Current Actual speed may differ from the set speed due to Expansion Bus use, or another forced change

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[?]

Group NameRW76543210DescriptionHD
Issue 2 keyboard■■ •Enable Issue 2 keyboard■0
NextSound • Enable Multiple PSGs*■0
Timex Video Port Control■■ • Enable read of Port FFh (Timex)**■0
DACs Control • Enable DACs (A-B-C-D)■0
Internal Speaker Control■■ • Enable Internal Speaker■1
PSG Stereo Mode Control■■ 0 Select ABC■0
1 Select ACB
Contention Control■■ • Disable RAM and Port Contention0
128K Banking Unlock Control■■• Unlock Port 7FFDh D5 (Unlocked = 1)0

* Currently selected PSG is frozen when disabled
** Enabling Timex Video Port read hides the floating bus on FFh

NextREG 09 (09h) – Peripheral 4 Settings

Group NameRWData BitsDescriptionHD
76543210
Scanline Strength■■ 00Scanlines off
01Scanlines at 50%
10Scanlines at 25%
11Scanlines at 12.5%
HDMI audio output Control■■ • HDMI audio mute■0
divMMC mapRAM bit Control■■ • Reset bit 6 port E3h (Read is always 0)
Sprite Lockstep Control■■ • Enable Sprite ID Lockstep0
PSG 0 Mono Mode Control■■ • Enable Mono■0
PSG 1 Mono Mode Control■■ • Enable Mono■0
PSG 2 Mono Mode Control■■• Enable Mono■0

In Sprite Lockstep, NextREG 52 (34h) and Port 12347 (303Bh) are in Lockstep

NextREG 10 (0Ah) – Peripheral 5 Settings

Group NameRWData BitsDescriptionHD
76543210
Mouse resolution Control■■ 00Low DPI■
01Default
10Medium DPI
11High DPI
Reserved■■ 0 Reserved, must be 00
Mouse button swap Control■■ • Reverses (swaps) L & R mouse buttons■0
divMMC Automap Control■■ • Enables divMMC Automap■0
Reserved■■ 0 Reserved, must be 0■0
Multiface Type■■00 Multiface +3¹♦0
01 Multiface 128 v87.2²
10 Multiface 128 v87.12³
11 Multiface 1⁴

¹ Enables port 3Fh, disables port BFh
² Enables port BFh, disables port 3Fh
³ Enables port 9Fh, disables port 1Fh
⁴ Enables port 9Fh, disables port 1Fh

NextREG 11 (0Bh) – Joystick Port Mode Selection

Group NameRWData BitsDescriptionHD
76543210
Parameter (Bit Bang)■■ •Copied to pin 7 of the active connector¹1
Parameter (Clock) 0Hold high when clock becomes high
1Run²
Parameter (UART) 0Redirect ESP UART_0 to connector³
1Redirect Pi UART_1 to connector³
Reserved■■ 0 0 0 Reserved, must be 00
I/OMode Control■■ 00 Bit Bang0
01 Clock
10 UART on left joystick port
11 UART on right joystick port
Reserved■■ 0 Reserved, must be 00
Joystick Port Mode Selection■■0 Joysticks Enabled0
1 I/O Mode Enabled

¹ The state of output pin 7 is stored internally in a register and is retained across changing modes and while I/O is disabled
² CTC Ch. 3 is currently used to drive pin 7 in clock mode. Frequency= fCTC3 ÷2
³ Tx out on pin 7, Rx in from pin 9, CTS_n in from pin 6. CTS_n is only active if the selected UART is in hardware flow control mode
* While in I/O mode, keyboard joystick types (Sinclair, Cursor etc) produce no readings but the current state of pins can still be read via the Kempston ports. When leaving I/O mode, joystick operation resumes after approximately 64 scanlines have passed

NextREG 14 (0Eh) – Core Version (Sub minor number)

Group NameRWData BitsDescriptionHD
76543210
Sub Minor Number■••••••••Core Sub Minor Version Number

See NextREG 01 (01h) for Major and Minor Core Version

NextREG 15 (0Fh) – Board ID

Group NameRWData BitsDescriptionHD
76543210
Board Revision■ 0000ZX Spectrum Next Issue 2¹
0001ZX Spectrum Next Issue 3¹
0010ZX Spectrum Next Issue 4²
Reserved■ 0 0 0 0 Reserved

¹ XC6SLX16-2FTG256, 128 Mbit W25Q128JV Flash, 24-bit SPI, 64K*8 Core size
² XC7A15T-1CSG324, 256 Mbit MX25L25645G Flash, 32-bit SPI, 64K*34 Core size

[?]

Group NameRW76543210DescriptionH[?]
NMI Button State Flag■ •NMI Button Pressed[?]
Drive Button State Flag■ • Drive Button Pressed[?]
■ ••••• Core ID (0-31)
Reserved■ 0 Reserved, must be 0[?]
Core ID■ •••••Core ID (0-31)♦[?]
Reserved■ 0 0 Reserved, must be 0[?]
Start Core■• Reboot FPGA using selected core[?]

Core ID with D0 through D4 can be set in configuration mode only

NextREG 17 (11h) – Video Timing

Group NameRWData BitsDescriptionH[?]
76543210
VGA Timing■■ 000Base VGA timing, clk28 = 28000000♦[?]
001VGA setting 1, clk28 = 28571429
010VGA setting 2, clk28 = 29464286
011VGA setting 3, clk28 = 30000000
100VGA setting 4, clk28 = 31000000
101VGA setting 5, clk28 = 32000000
110VGA setting 6, clk28 = 33000000
111Digital, clk28 =27000000
Reserved■■ 0 0 0 0 0 Reserved, must be 0[?]

50 Hz / 60 Hz depends on NextREG 05 (05h):D2
NextREG writable in configuration mode only

NextREG 18 (12h) – Layer 2 Active RAM Bank

Group NameRWData BitsDescriptionH[?]
76543210
Layer 2 Active RAM Bank■■ •••••••Starting 16K RAM Bank[?]
Reserved■■ 0 Reserved, must be 0[?]

Soft reset resets the default to 8. NextZXOS changes that to 9

NextREG 19 (13h) – Layer 2 Shadow RAM Bank

Group NameRWData BitsDescriptionH[?]
76543210
Layer 2 Shadow RAM Bank■■ •••••••Starting 16K RAM Bank[?]
Reserved■■ 0 Reserved, must be 0[?]

Soft reset resets the default to 11. NextZXOS changes that to 12

NextREG 20 (14h) – Global Transparency Colour

Group NameRWData BitsDescriptionH[?]
76543210
Global Transparency Mask■■••••••••8-bit colour value[?]

Default value upon soft reset is E3h (227)
This value is 8-bit; the transparency colour is compared against the MSB of the actual 9-bi[?] colour; as such, two colours (with either value of B0) are made transparent
This setting only applies to Layer 2, Layer 0 and Layer 1. Sprites use NextREG 75 (4Bh) and Layer 3 uses NextREG 76 (4Ch) for transparency except in text mode

NextREG 21 (15h) – Sprite and Layer System Setup

Group NameRWData BitsDescriptionH[?]
76543210
Sprite Engine Control■■ •Enable Sprites[?]
Sprite Extended Area Control■■ • Enable Sprites over border[?]
Set Layer Priority■■ 000 S L U[?]
001 L S U
010 S U L
011 L U S
100 U S L
101 U L S
110 (U|T)S(T|U)(B+L) combined¹
111 (U|T)S(T|U)(B+L) combined¹
Sprite Border Clipping■■ • Enable Sprite Clipping in over border mode[?]
Sprite Priority■■ 0 Sprite 127 on top[?]
1 Sprite 0 on top
LoRes Control■■• Enable LoRes[?]

1 Colours Clamped to [0,7]
ULA means all ULA modes: Layers 0 and all Layer 1 types. Value upon soft reset is 000

NextREG 22 (16h) – Layer 2 Horizontal Scroll Control LSB

Group NameRWData BitsDescriptionH[?]
76543210
X Offset LSB■■••••••••8-bit value of X Offset LSB (0 – 511)[?]

MSB is in NextREG 113 (71h)

NextREG 23 (17h) – Layer 2 Vertical Scroll Control

Group NameRWData BitsDescriptionH[?]
76543210
Y Offset■■••••••••8-bit value of Y Offset[?]

NextREG 24 (18h) – Layer 2 Clip Window Definition

Group NameRWData BitsDescriptionH[?]
76543210
Coordinate (Xbeg,Xend,Ybeg,Yend)■■••••••••8-bit value of Xbeg,Xend,Ybeg,Yend coordinate¹[?]

¹ 1st Write Xbeg position – *Resets to 0
2nd Write Xend position – *Resets to 255
3rd Write Ybeg position – *Resets to 0
4rh Write Yend position – *Resets to 191
Reads do not advance the clip coordinate – Use NR 28 (1Ch) to find out the current clip coordinate or to set the clip coordinate to Xbeg. The X coordinates are internally doubled fo[?] higher resolution modes. This means that Xend =159 covers the full 320 resolution.

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[?]

Group NameRW76543210DescriptionHD
Coordinate (Xbeg,Xend,Ybeg,Yend)■■••••••••8-bit value Xbeg,Xend,Ybeg,Yend coordinate¹*

1 1st Write Xbeg position – *Resets to 0
2nd Write Xend position – *Resets to 255
3rd Write Ybeg position – *Resets to 0
4rh Write Yend position – *Resets to 191
Reads do not advance the clip position – Use NR 28 (1Ch) D2:D3 to read the position. If need be, write to NR 28 (1Ch):D1 to reset the clip index. When the clip window is enabled for sprites in over border mode, the X coordinates are internally doubled and the clip window origin is moved to the sprite origin inside the border

NextREG 26 (1Ah) – Layer 0 (ULA/LoRes) Clip Window Definition

Group NameRWData BitsDescriptionHD
76543210
Coordinate (Xbeg,Xend,Ybeg,Yend)■■••••••••8-bit value Xbeg,Xend,Ybeg,Yend coordinate¹*

1 1st Write Xbeg position – *Resets to 0
2nd Write Xend position – *Resets to 255
3rd Write Ybeg position – *Resets to 0
4rh Write Yend position – *Resets to 191
Reads do not advance the clip position – Use NR 28 (1Ch) D4:D5 to read the position. If need be, write to NR 28 (1Ch):D2 to reset the clip index
NOTE: LoRes may get a separate clip window in the future

NextREG 27 (1Bh) – Layer 3 (Tilemap) Clip Window Definition

Group NameRWData BitsDescriptionHD
76543210
Coordinate (Xbeg,Xend,Ybeg,Yend)■■••••••••8-bit value Xbeg,Xend,Ybeg,Yend coordinate¹*

¹ 1st Write Xbeg position – *Resets to 0
2nd Write Xend position – *Resets to 159
3rd Write Ybeg position – *Resets to 0
4rh Write Yend position – *Resets to 255
Reads do not advance the clip position – NR 28 (1Ch) D6:D7 reads the position. If need be, write to NR 28 (1Ch):D3 to reset the clip index and then do consecutive writes and reads to get to the value you're searching for. The X coordinates are internally doubled

NextREG 28 (1Ch) – Clip Windows Control

Group NameRWData BitsDescriptionHD
76543210
Layer 2 Clip Index■ ••Layer 2 Clip Index (0 – 3)
Sprites Layer Clip Index■ •• Sprites Clip Index (0 – 3)
Layer 0 / 1 Clip Index■ •• ULA / Timex Clip Index (0 – 3)
Layer 3 Clip Index■•• Tilemap Clip Index (0 – 3)
Reserved■ 0 0 0 0 Reserved, must be 0
Layer 2 Clip Index Reset enable■ •1 to Reset the Layer 2 Clip Index
Sprites Clip Index Reset enable■ • 1 to Reset the Sprites Clip Index
Layer 0/1 Clip Idx Reset enable■ • 1 to Reset the ULA/Timex Clip Index
Layer 3 Clip Idx Reset enable■ • 1 to Reset the Tilemap Clip Index

NOTE: This NextREG may change in the future

NextREG 30 (1Eh) – Active Video Line MSB

Group NameRWData BitsDescriptionHD
76543210
Active Video Line (MSB)■ •1 for lines above 255 else 0
Reserved■ 0 0 0 0 0 0 0 Reserved, must be 0

NextREG 31 (1Fh) – Active Video Line LSB

Group NameRWData BitsDescriptionHD
76543210
Active Video Line (LSB)■••••••••Active Video Line (LSB)

NextREG 32 (20h) – Maskable Interrupt Generation

Group NameRWData BitsDescriptionHD
76543210
CTC■■ 0000No CTC interrupt generated
•Generate CTC 0 interrupt
• Generate CTC 1 interrupt
• Generate CTC 2 interrupt
• Generate CTC 3 interrupt
Reserved■■ 0 0 Reserved, must be 0
ULA■■ • Generate ULA interrupt
Line■■• Generate Line interrupt

* Set bits on R indicate whether an interrupt occurred or is pending – alias of bits in NextREGs 200 - 202 (C8h - CAh)
* Set bits on W always generate a maskable interrupt ignoring enables – NextREGs 196 - 198 (C4h - C6h)

NextREG 34 (22h) – Line Interrupt Control

Group NameRWData BitsDescriptionHD
76543210
Line Interrupt Value MSB■■ •MSB of line number0
Line Interrupt Control■■ • Enable Line Interrupt*0
ULA Interrupt Control■■ • Disable ULA Interrupt*0
Reserved■ 0 0 0 0 0 Reserved, must be 0
■ 0 0 0 0 Reserved, must be 0
ULA Interrupt Signal■• ULA is currently asserting interrupt

* Aliases of interrupt enable bits in NextREG 196 (C4h)

NextREG 35 (23h) – Line Interrupt Value LSB

Group NameRWData BitsDescriptionHD
76543210
Line Interrupt Value LSB■■••••••••Lower 8-bits of line number0

NextREG 36 (24h) – Reserved

Protection against OUT 3Bh, A – See DISCiPLE disk interface for example.
In legacy modes set selected NextREG to 36 (24h)

[?]

Group NameRW76543210DescriptionHD
X Offset■■••••••••8-bit value of X Offset (0-255)0

This setting refers to all ULA modes except Layer 1,0 – LoRes
NextREG 104 (68h):D2 adds a half pixel to the scroll

NextREG 39 (27h) – ULA Vertical Scroll Control

Group NameRWData BitsDescriptionHD
76543210
Y Offset■■••••••••8-bit value of Y Offset (0-191)0

This setting refers to all ULA modes except Layer 1,0 – LoRes

NextREG 40 (28h) – Stored Palette Value and PS/2 Keymap Address MSB

Group NameRWData BitsDescriptionHD
76543210
Stored Palette value■••••••••See NextREG 68 (44h)
PS/2 Keymap Address MSB■ •MSB of value in NR 41 (29h)
Keymap Selection■0 Select PS/2 Keymap0
1 Select key joystick
Reserved■ 0 0 0 0 0 0 Reserved, must be 0

NextREG 41 (29h) – PS/2 Keymap Address LSB

Group NameRWData BitsDescriptionHD
76543210
PS/2 Keymap Address LSB■••••••••8-bit value (0-255)0

NextREG 42 (2Ah) – PS/2 Keymap Data MSB

Group NameRWData BitsDescriptionHD
76543210
PS/2 Keymap Data MSB■ •PS/2 Keymap Data MSB*
Reserved■ 0 0 0 0 0 0 0 Reserved, must be 0

* Not currently used by hardware. Write 0

NextREG 43 (2Bh) – PS/2 Keymap Data LSB

Group NameRWData BitsDescriptionHD
76543210
PS/2 Keymap Data LSB■••••••••8-bit value (0-255)

A write causes the data to be written and auto-increments the Keymap Address

NextREG 44 (2Ch) – DAC B Mirror (Left) / I²S Left Sample MSB

Group NameRWData BitsDescriptionHD
76543210
I²S Left Sample MSB■••••••••8-bit value (0-255)
8-bit sample Left DAC B■••••••••8-bit value*

* A soft reset sets a value of 128 (80h)
The I²S Left Sample LSB is latched and can be read from NextREG 45 (2Dh) later

NextREG 45 (2Dh) – DAC A+D Mirror (Mono) / I²S Sample LSB

Group NameRWData BitsDescriptionHD
76543210
I²S Last Sample LSB■••••••••8-bit value (0-255)
8-bit sample DACs A + D■••••••••8-bit value*

* A soft reset sets a value of 128 (80h)
Returns the LSB of last sample read from NextREG 44(2Ch) or NextREG 46(2Eh)

NextREG 46 (2Eh) – DAC C Mirror (Right) / I²S Right Sample MSB

Group NameRWData BitsDescriptionHD
76543210
I²S Right Sample MSB■••••••••8-bit value (0-255)
8-bit sample Right DAC C■••••••••8-bit value*

* A soft reset sets a value of 128 (80h)
The I²S Right Sample LSB is latched and can be read from NextREG 45 (2Dh) later

NextREG 47 (2Fh) – Layer 3 (Tilemap) Horizontal Scroll Control MSB

Group NameRWData BitsDescriptionHD
76543210
Layer 3 X Scroll Offset MSB■■ ••Tilemap X Scroll Offset MSB0
Reserved■ 0 0 0 0 0 0 Reserved, must be 0

Meaningful range: 0 to 319 in 40 tiles mode, 0 to 639 in 80 tiles mode

NextREG 48 (30h) – Layer 3 (Tilemap) Horizontal Scroll Control LSB

Group NameRWData BitsDescriptionHD
76543210
X Offset LSB■■••••••••8-bit value (0-255)0

Meaningful range: 0 to 319 in 40 tiles mode, 0 to 639 in 80 tiles mode

NextREG 49 (31h) – Layer 3 (Tilemap) Vertical Scroll Control

Group NameRWData BitsDescriptionHD
76543210
Y Offset■■••••••••8-bit value (0-255)0

NextREG 50 (32h) – Layer 1,0 (LoRes) Horizontal Scroll Control

Group NameRWData BitsDescriptionHD
76543210
X Offset■■••••••••8-bit value of X Offset (0-255)0

Layer 1,0 (LoRes) scrolls in half-pixels at the same resolution and smoothness as Layer 2

NextREG 51 (33h) – Layer 1,0 (LoRes) Vertical Scroll Control

Group NameRWData BitsDescriptionHD
76543210
Y Offset■■••••••••8-bit value of Y Offset (0-191)0

Layer 1,0 (LoRes) scrolls in half-pixels at the same resolution and smoothness as Layer 2

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[?]

Group NameRW76543210DescriptionHD
When NR09:D4 is set■■ •••••••Sprite number¹ / Pattern Number²
• Pattern Address Offset³

The above applies only when the sprites port is in Lockstep and effectively performs an OUT to port 12347 (303Bh) with the same value otherwise the section below applies

When NR09:D4 is NOT set■■ 0•••••••Sprite number¹

1 Values are 0 to 127
2 Values are 0 to 63
3 Adds 128 to pattern address
This register selects which sprite has its attributes connected to the registers that follow:
NextREG 53 (36h) – NextREG 57 (39h) and their auto-incremented counterparts
NextREG 117 (75h) – NextREG 121 (79h)

NextREG 53 (35h) – Sprite Attribute 0

Group NameRWData BitsDescriptionHD
76543210
X Coordinate LSB■••••••••Sprite X Coordinate LSB

MSB is in NextREG 55 (37h):D0

NextREG 54 (36h) – Sprite Attribute 1

Group NameRWData BitsDescriptionHD
76543210
Y Coordinate LSB■••••••••Sprite Y Coordinate LSB

MSB is in NextREG 57 (39h):D0

NextREG 55 (37h) – Sprite Attribute 2

Group NameRWData BitsDescriptionHD
76543210
Sprite Attribute 2■eeeedcbaSee notes

a For relative sprites: Indicates that e is relative to the anchor's palette offset
For normal sprites: Sprite's X Coordinate MSB (See NextREG 53 (35h) for LSB)
b 90° Clockwise Rotation Control (0 = No, 1 = Yes)
c Vertical Mirror Control (0 = No, 1 = Yes)
d Horizontal Mirror Control (0 = No, 1 = Yes)
e 4-bit palette offset
Rotation is applied before mirroring

NextREG 56 (38h) – Sprite Attribute 3

Group NameRWData BitsDescriptionHD
76543210
Sprite Attribute 3■cbaaaaaaSee notes

a Sprite pattern to use. Possible values = 0 to 63
b Attribute 4 switch (0 = No, 1 = Yes)
If b = 0 then the sprite is fully described by Attributes 0 to 3. The sprite pattern is an 8-bit one identified by pattern a and is an anchor and cannot be made relative. Sprite display behaves as if Attribute 4 = 0
If b = 1 then the sprite is further described by Attribute 4 that follows in NextREG 57 (39h)
c Visibility Control (0 = Invisible, 1 = Visible)

NextREG 57 (39h) – Sprite Attribute 4

Group NameRWData BitsDescriptionHD
76543210
Sprite Attribute 4■fedccbbaSee notes

a For relative sprites: Indicates that the sprite pattern number is relative to the anchor's
For normal sprites: Sprite's Y Coordinate MSB (See NextREG 54 (36h) for LSB)
b For normal and relative, composite type sprites indicates X direction Magnification:
(00 = 1x, 01 = 2x, 10 = 4x, 11 = 8x)
For relative, unified type sprites it's 0
c For normal and relative, composite type sprites indicates Y direction Magnification:
(00 = 1x, 01 = 2x, 10 = 4x, 11 = 8x)
For relative, unified type sprites it's 0
d For normal sprites, indicates that the attached relative sprites are: 0 for Composite, 1 for Unified
For relative sprites contains the 7th pattern bit if the sprite pattern is 4-bit.
e For normal sprites contains the 7th pattern bit if the sprite pattern is 4-bit.
For relative sprites it's 1.
f 4-bit pattern switch: 1 if the sprite pattern is 4-bit otherwise 0
{f,e} must not equal {0,1} as this combination is used to indicate a relative sprite. See notes above

NextREG 64 (40h) – Palette Index Select

Group NameRWData BitsDescriptionHD
76543210
Palette Index Select■■••••••••Palette index number

Selects the palette index to change the associated colour
For ULA only, INKs are mapped to indices 0 through 7, BRIGHT INKs to indices 8 through 15, PAPERs to indices 16 through 23 and BRIGHT PAPERs to indices 24 through 31
In EnhancedULA mode, INKs come from a subset of indices from 0 through 127 and PAPERs from a subset of indices from 128 through 255.
The number of active indices depends on the number of attribute bits assigned to INK and PAPER out of the attribute byte
In ULAplus mode, the last 64 entries (indices 192 to 255) hold the ULAplus palette
The ULA always takes border colour from PAPER for standard ULA and EnhancedULA

NextREG 65 (41h) – 8-bit Palette Data

Group NameRWData BitsDescriptionHD
76543210
8-bit Palette Entry■■••••••••Colour entry in RRRGGGBB format

The lower blue bit of the 9-bit internal colour will be the logical OR of Bits 0 and 1 of the 8-bit entry. After each write, the palette index is auto-incremented to the next index if the auto-increment has been enabled in NextREG 67 (43h):D7
Reads do not auto-increment the index. Any other bits associated with the index will be zeroed

NextREG 66 (42h) – EnhancedULA Attribute Byte Format

Group NameRWData BitsDescriptionHD
76543210
Attribute Byte Format■■••••••••Attrbute byte's INK representation mask*

* Soft reset defaults to 7
Not set bits, indicate PAPER. Acceptable values are made by setting each bit from 0 on, in sequence: (1,3,7,15,31,63,127 and 255) which effectively splits the attribute byte setting the INKs from the right side and the PAPERs from what's left. INKs are mapped from Index 0 onwards on the palette while PAPERs and BORDER are mapped from Index 128 onwards
A full value of 255 will set all colours to INK (Full INK mode) and PAPER and BORDER are taken from the fallback colour defined in NextREG 74 (4Ah)
If the mask is not one of those listed above, the INK is still the result of logically ANDing the mask with the attribute byte but the PAPER and BORDER will be taken from the fallback colour
Example:
00111011 will be ANDed with the attribute byte to form the INK index and PAPER will come from the fallback colour

NextREG 67 (43h) – Palette Control

Group NameRWData BitsDescriptionH[?]
76543210
EnhancedULA control■■ •Enable EnhancedULA[?]
Active ULA¹ Palette■■ 0 First Palette[?]
1 Second Palette
Active Layer 2 Palette■■ 0 First Palette[?]
1 Second Palette
Active Sprites Palette■■ 0 First Palette[?]
1 Second Palette
Palette Select for Read/Write■■ 000 Layers 0/1 (ULA) First[?]
100 Layers 0/1 (ULA) Second
001 Layer 2 First
101 Layer 2 Second
010 Sprites First
110 Sprites Second
011 Layer 3 (Tilemap) First
111 Layer 3 (Tilemap) Second
Palette Auto-increment Control■■• Disable Palette Write Auto-increment[?]

* After a soft reset defaults to 000
¹ ULA refers to all ULA modes (Layers 0 and 1)

NextREG 68 (44h) – 9-bit Palette Data

Group NameRWData BitsDescriptionH[?]
76543210
MSB Colour (1st Write) Non L2■••••••••MSB (RRRGGGBB) format – non L2 palette[?]
LSB Blue (2nd Write) Non L2■■ •LSB B format – non L2 palette
Reserved Non L2■ 0 0 0 0 0 0 0 Reserved, must be 0 – non L2 palette
MSB Colour (1st Write) L2■••••••••MSB (RRRGGGBB) format – L2 palette[?]
LSB Blue + Priority L2 (2nd W)■■• •L2 priority (D7) and LSB B(D0)[?]
Reserved L2■ 0 0 0 0 0 0 Reserved, must be 0 L2 palette[?]

9-bit Palette Data is entered in two consecutive writes; the second write auto-increments the palette index if auto-increment is enabled in NextREG 67 (43h):D7
If writing an L2 palette, the second write's D7 holds the L2 priority bit which if set (1) brings the colour defined at that index on top of all other layers. If you also need the same colour in regular priority (for example: for environmental masking) you will have to set it up again, this time with no priority
Reads return the second byte and do not auto-increment
Writes to NextREGs 64, 65 and 67 (40h, 41h and 43h) reset to the 1st write

NextREG 74 (4Ah) – Fallback Colour Value

Group NameRWData BitsDescriptionH[?]
76543210
Fallback Colour■■••••••••8-bit colour if all layers are transparent[?]

* Soft reset sets the default fallback to 227 (E3h) as it must be the same for when ULAplus programs hit the transparent colour, otherwise nothing will be displayed

NextREG 75 (4Bh) – Sprite Transparency Index

Group NameRWData BitsDescriptionH[?]
76543210
Transparency Index■■••••••••Sprite colour index treated as transparent[?]

* Soft reset defaults to 227 (E3h)
For 4-bit sprites, only 4-bits are used (from D0 to D3)
For example for 8-bit transparency index 227 (E3h) the 4-bit equivalent will be 03 (03h)

NextREG 76 (4Ch) – Layer 3 (Tilemap) Transparency Index

Group NameRWData BitsDescriptionH[?]
76543210
Transparency Index■■ ••••4-bit index treated as transparent[?]
Reserved■■ 0 0 0 0 Reserved, must be 0[?]

* Soft reset defaults to 15 (0Fh)

NextREG 80 (50h) – MMU Slot 0 Control

Group NameRWData BitsDescriptionH[?]
76543210
MMU Slot 0 Control■■••••••••8K RAM page for address 0000h–1FFFh[?]

* Default 255 (FFh)
Pages range from 0 to 223 on a fully expanded Next. A value of 255 (FFh) makes the ROM become visible

NextREG 81 (51h) – MMU Slot 1 Control

Group NameRWData BitsDescriptionH[?]
76543210
MMU Slot 1 Control■■••••••••8K RAM page for address 2000h–3FFFh[?]

* Default 255 (FFh)
Pages range from 0 to 223 on a fully expanded Next. A value of 255 (FFh) makes the ROM become visible

NextREG 82 (52h) – MMU Slot 2 Control

Group NameRWData BitsDescriptionH[?]
76543210
MMU Slot 2 Control■■••••••••8K RAM page for address 4000h–5FFFh[?]

* Default 10 (0Ah)
Pages range from 0 to 223 on a fully expanded Next

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NextREG 83 (53h) – MMU Slot 3 Control

Group NameRWData BitsDescriptionHD
76543210
MMU Slot 3 Control■■••••••••8K RAM page for address 6000h–7FFFh*

* Default 11 (0Bh) – Pages range from 0 to 223 on a fully expanded Next

NextREG 84 (54h) – MMU Slot 4 Control

Group NameRWData BitsDescriptionHD
76543210
MMU Slot 4 Control■■••••••••8K RAM page for address 8000h–9FFFh*

* Default 4 (04h) – Pages range from 0 to 223 on a fully expanded Next

NextREG 85 (55h) – MMU Slot 5 Control

Group NameRWData BitsDescriptionHD
76543210
MMU Slot 5 Control■■••••••••8K RAM page for address A000h–BFFFh*

* Default 5 (05h) – Pages range from 0 to 223 on a fully expanded Next

NextREG 86 (56h) – MMU Slot 6 Control

Group NameRWData BitsDescriptionHD
76543210
MMU Slot 6 Control■■••••••••8K RAM page for address C000h–DFFFh*

* Default 0 (00h) – Pages range from 0 to 223 on a fully expanded Next

NextREG 87 (57h) – MMU Slot 7 Control

Group NameRWData BitsDescriptionHD
76543210
MMU Slot 7 Control■■••••••••8K RAM page for address E000h–FFFFh*

* Default 1 (01h) – Pages range from 0 to 223 on a fully expanded Next

NextREG 96 (60h) – Copper Data 8-bit Write

Group NameRWData BitsDescriptionHD
76543210
Copper Instruction 8-bit■••••••••Byte to write to copper instruction memory

Each Copper Instruction is two-bytes long. After a write, the Copper address is auto-incremented to the next memory position

NextREG 97 (61h) – Copper Address LSB

Group NameRWData BitsDescriptionHD
76543210
Copper memory address LSB■■••••••••Copper instruction memory address (LSB)0

Copper memory addresses range over 0 through 2047 (7FFh)

NextREG 98 (62h) – Copper Control

Group NameRWData BitsDescriptionHD
76543210
Copper Memory Address MSB■■ •••Copper Instruction Memory Address (MSB)0
Copper Start Control■■00 Copper fully stopped*
01 Copper start, exec from 0, loop
10 Copper start, exec from last, loop
11 Copper start, exec from 0, rest. at raster 0,0

* Soft reset defaults to 000
Copper memory addresses range from 0 through 2047 (7FFh)
Note: Writing the same copper start control value does not reset the copper

NextREG 99 (63h) – Copper Data 16-bit Write

Group NameRWData BitsDescriptionHD
76543210
Copper data■••••••••1st write MSB, 2nd write LSB0

The 16-bit value is written in pairs. The first 8-bits are the MSB and are destined for an even copper instruction address. The second 8-bits are the LSB and are destined for an odd copper instruction address
After each write, the copper address is auto-incremented to the next memory position.
After a write to an odd address, the entire 16-bits is written to copper memory at once

NextREG 100 (64h) – Vertical Line Count Offset

Group NameRWData BitsDescriptionHD
76543210
Line counter offset■■••••••••Offset added to the vertical line counter*

* Affects Copper, line interrupt and active line count
Normally the ULA's pixel row 0, aligns with vertical line count 0. With a non-zero offset, the ULA's pixel row 0 will align with the vertical line offset. For example if the offset is 32 then vertical line 32 will correspond to the first pixel row in the ULA and vertical line 0 will align with the first pixel row of Layer 3 (Tilemap) and the Sprite Layer
NOTE: Since a change in offset takes effect when the ULA reaches row 0, the change can take up to one frame to occur

NextREG 104 (68h) – ULA Control

Group NameRWData BitsDescriptionHD
76543210
Stencil Mode control■■ •Enable Stencil Mode¹0
Reserved■ 0 Reserved, must be 00
ULA Half-Pixel Scroll■■ • ULA Half-Pixel Scroll enabled²0
ULAplus Control■■ • ULAplus Enabled0
Extended keys in 8x5 matrix■■ • Cancel entries in matrix for extended keys0
Blend Colour Used in SLU modes 6 & 7■■ 00 ULA Colour0
10 ULA + Tilemap mix
11 Tllemap Colour
01 No Colour Blending
Output Control■■• Disable ULA output0

1 When both the ULA and Layer 3 (Tilemap) are enabled, if either are transparent, the result is transparent otherwise the result is a logical AND of both colours
2 Setting may change

NextREG 105 (69h) – Display Control 1

Group NameRWData BitsDescriptionHD
76543210
Port 255 (FFh) “Timex” alias■■ ••••••Port 255 (FFh) alias
Port 32765 (7FFDh):D3 alias■■ • ULA Shadow Display Enable
Port 4667 (123Bh):D1 alias■■• Layer 2 Enable

NextREG 106 (6Ah) – Layer 1,0 (LoRes) Control

Group NameRWData BitsDescriptionHD
76543210
LoRes | ULAplus palette Offset■■ ••••LoRes Palette Offset0
••ULAplus Palette Offset0
Radastan Mode DFILE Source■■ • Timex DFILE source¹0
LoRes mode■■ • Radastan Mode Enable0
Reserved■■ 0 0 Reserved, must be 0

1 Layer 1,0 (LoRes) occupies both Timex display files but Radastan mode has only half the colour depth thus occupies only one DFILE – at either 16384 (4000h) or 24576 (6000h). When this bit is set, the source DFILE used is the opposite of the ULA so that Radastan can co-exist with the normal Layer 0 (ULA) screen

NextREG 107 (6Bh) – Layer 3 (Tilemap) Control

Group NameRWData BitsDescriptionHD
76543210
Layer 3 Priority■■ •Tilemap on top of ULA Enable0
512 Tile mode Control■■ • Activate 512 Tile mode¹0
Reserved■■ 0 Reserved, must be 00
Text mode Control■■ • Text mode Enable0
Layer 3 palette Select■■ 0 Palette 00
1 Palette 1
Attribute Entry Control■■ • Attribute entry Disable²0
Layer 3 Size Control■■ 0 40 x 320
1 80 x 32
Layer 3 Control■■• Tilemap Enable0

1 If this bit is set, NextREG 108 (6Ch):D0 changes meaning
2 If this bit is set then the Layer 3 tilemap entries are only a single byte Tile ID and the attribute byte comes from NextREG 108 (6Ch) instead

NextREG 108 (6Ch) – Default Layer 3 (Tilemap) Attribute*

Group NameRWData BitsDescriptionHD
76543210
If 512 Tile mode is disabled■■ •ULA over Layer 30
If 512 Tile mode is enabled■■ •Bit 8 of the tile number
Rotate 90° Control■■ • Rotate0
Y Mirror Control■■ • Y Mirror0
X Mirror Control■■ • X Mirror0
Palette Offset■■•••• Palette Offset0

* Active if NextREG 107 (6Bh):D5 is set. If NextREG 107 (6Bh):D3 is set, the palette offset is extended to D7:D1 replacing the rotate and mirror bits

NextREG 110 (6Eh) – Layer 3 (Tilemap) Base Address

Group NameRWData BitsDescriptionHD
76543210
MSB of Layer 3 base address in Banks 5 & 7■■ 0••••••Address in bank 5 or bank 7 – Entered*
■■• together with bit 7 – bit 6 is 0

* Soft Reset value is 108 (6Ch) read as 44 (2Ch)
Writes are the MSB of an address in bank 5 16384 - 32767 (4000h – 7FFFh) or in bank 7 49152 - 65535 (C000h – FFFFh) with D6 ignored and always read back as 0. This means tile definitions start on 256-byte boundaries
Bank 7 addresses wrap around its 8K boundary

NextREG 111 (6Fh) – Layer 3 (Tilemap) - Tile Definitions Base Address

Group NameRWData BitsDescriptionHD
76543210
MSB of Layer 3 Tile definitions base address in Banks 5 & 7■■ 0••••••Address in bank 5 or bank 7 – Entered*
■■• together with bit 7 – bit 6 is 0

* Soft Reset value is 76 (4Ch) read as 12 (0Ch)
Writes are the MSB of an address in bank 5 16384 - 32767 (4000h – 7FFFh) or in bank 7 49152 - 65535 (C000h – FFFFh) with D6 ignored and always read back as 0. This means tile definitions start on 256-byte boundaries
Bank 7 addresses wrap around its 8K boundary

NextREG 112 (6Ah) – Layer 2 Resolution Control*

Group NameRWData BitsDescriptionHD
76543210
Layer 2 Palette Offset■■ ••••Layer 2 4-bit Palette Offset0
Layer 2 Resolution Select**■■ 00 256 x 192 x 8bpp (Layer 2 standard)0
01 320 x 256 x 8bpp (Layer 2, Mode 2)
10 640 x 256 x 4bpp (Layer 2, Mode 3)
Reserved■■ 0 0 Reserved, must be 0

* The Layer 2 screen occupies 48K or 80K, which is stored in 3 consecutive 16 KB banks for 256 x 192 x 8bpp or 5 consecutive banks for 320 x 256 and 640 x 256 resolutions. When in NextZXOS/NextBASIC, banks 9 - 11 are used for the visible and shadow Layer 2(,0) screen (after power-on, the hardware default to banks 8 - 10 for displayed and 11 - 13 for shadow screen but this gets modified by NextZXOS – See Chapter 23). These can be set using Layer 2 RAM Page NextREG 18 (12h) and Layer 2 RAM Shadow Page NextREG 19 (13h) (avoid banks 5, 7 and 8 to be used as Layer 2 screen, unless you are familiar with SRAM and BRAM of the board and how the ULA screen memory has special treatment in Next's FPGA)

** Each pixel of Layer 2 is assigned 1 byte (8-bits) (in 8bpp modes) or 1 nibble (4-bits) (in 640 x 256 x 4bpp mode) of video memory. This means Layer 2 consumes a total of either 48K or 80K of memory. The memory is divided in 16K "strips" filling one standard Spectrum bank. In 256x192 mode the strips are horizontal so that 16K represent 64 vertical lines on the display. In 320x256 and 640x256 modes the strips are vertical so that each 16K corresponds to 64 or 128 columns respectively – See Chapters 15 and 16

NextREG 113 (71h) – Layer 2 Horizontal Scroll Control MSB

Group NameRWData BitsDescriptionHD
76543210
X Coordinate MSB■■ •Layer 2 X Coordinate MSB
Reserved■■ 0 0 0 0 0 0 0 Reserved, must be 0

LSB is in NextREG 22 (16h)

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NextREG 117 (75h) – Sprite Attribute 0 (Auto-incrementing)

Group NameRWData BitsDescriptionHD
76543210
X Coordinate LSB■••••••••Sprite X Coordinate LSB

Same as NextREG 53 (35h) but writes also auto-increment the sprite number

NextREG 118 (76h) – Sprite Attribute 1 (Auto-incrementing)

Group NameRWData BitsDescriptionHD
76543210
Y Coordinate LSB■••••••••Sprite Y Coordinate LSB

Same as NextREG 54 (36h) but writes also auto-increment the sprite number

NextREG 119 (77h) – Sprite Attribute 2 (Auto-incrementing)

Group NameRWData BitsDescriptionHD
76543210
Sprite Attribute 2■eeeedcbaSee notes

a,b,c,d,e: Same as NextREG 55 (37h) but writes also auto-increment the sprite number

NextREG 120 (78h) – Sprite Attribute 3 (Auto-incrementing)

Group NameRWData BitsDescriptionHD
76543210
Sprite Attribute 3■cbaaaaaaSee notes

a,b,c: Same as NextREG 56 (38h) but writes also auto-increment the sprite number

NextREG 121 (79h) – Sprite Attribute 4 (Auto-incrementing)

Group NameRWData BitsDescriptionHD
76543210
Sprite Attribute 4■fedccbbaSee notes

a,b,c,d,e,f: Same as NextREG 57 (39h) but writes also auto-increment the sprite number

NextREG 127 (7Fh) – User Register 0

Group NameRWData BitsDescriptionHD
76543210
User Register■■••••••••User Register*

* Soft reset defaults to 255 (FFh)

CAUTION: NextREG numbers above 127 (7Fh) are inaccessible to the Copper

NextREG 128 (80h) – Expansion Bus Enable

Group NameRWData BitsDescriptionHD
76543210
AFTER SOFT RESET (Copied into bits D4 through D7)
Memory Cycles and R̅O̅M̅C̅S̅■■ •Memory cycles Disable/ Ignore R̅O̅M̅C̅S̅■0
I/O Cycles and I̅O̅R̅Q̅U̅L̅A̅■■ • I/O cycles Disable / Ignore I̅O̅R̅Q̅U̅L̅A̅■0
divMMC R̅O̅M̅C̅S̅ ROM Enable■■ • ROM from divMMC banks 14/15 Enable■0
Expansion bus Enable■■ • Expansion bus Enable■0
IMMEDIATE
Memory Cycles and R̅O̅M̅C̅S̅■■ • Memory cycles Disable/ Ignore R̅O̅M̅C̅S̅■0
I/O Cycles and I̅O̅R̅Q̅U̅L̅A̅■■ • I/O cycles Disable / Ignore I̅O̅R̅Q̅U̅L̅A̅■0
divMMC R̅O̅M̅C̅S̅ ROM Enable■■ • ROM from divMMC banks 14/15 Enable■0
Expansion bus Enable■■• Expansion bus Enable■0

NextREG 129 (81h) – Expansion Bus Control

Group NameRWData BitsDescriptionHD
76543210
MAX CPU Speed when Expansion Bus is enabled¹■■ 003.5 MHz■*
017 MHz
1014 MHz
1128 MHz
Propagate MAX CPU Clock ena.■■ • Propagate MAX CPU Clock at all times²■0
Disable Exp.Bus NMI Debounce■■ • Disables the NMI debounce³■0
ULA override control■■ • Allows peripherals to override ULA⁴■0
Exp. bus R̅O̅M̅C̅S̅ state flag■• R̅O̅M̅C̅S̅ asserted on Expansion Bus■0

* Hard reset defaults to 00
¹ Currently fixed at 00
² Applies even when the Expansion Bus is disabled
³ A value of 1 disables the Expansion BSus' NMI debounce as required by some peripherals like the Opus Discovery
⁴ A value of 1 allows peripherals to override the ULA on even port reads as equired by some peripherals like the Rotronics Wafadrive

NextREG 130 (82h) – Internal Port Decoding Control 1/4

Group NameRWData BitsDescriptionHD
76543210
Enable Timex■■ •Port FFh1
Enable Paging■■ • Port 7FFDh1
Enable Next Memory Paging■■ • Port DFFDh1
Enable +3 Paging■■ • Port 1FFDh1
Enable +3 Floating Bus■■ • +3 Floating bus1
Enable DMA■■ • Port 6Bh (DMA)1
Enable Kempston Port 1■■ • Port 1Fh (Kempston / MD 1)1
Enable Kempston Port 2■■• Port 37h (Kempston / MD 2)1

NextREG 131 (83h) – Internal Port Decoding Control 2/4

Group NameRWData BitsDescriptionHD
76543210
Enable divMMC■■ •Port E3h (divMMC Control)1
Enable Multiface■■ • Multiface (two variable ports)1
Enable I²C■■ • Ports 103Bh, 113Bh (I²C)1
Enable SPI■■ • Ports E7h, EBh (SPI)1
Enable UART■■ • Ports 133Bh, 143Bh, 153Bh,163Bh (UART)1
Enable Kempston Mouse■■ • Ports FADFh,FBDFh,FFDFh mouse*1
Enable Sprites■■ • Ports 57h,5Bh,303Bh (Sprites)1
Enable Layer 2■■• Port 123Bh (Layer2)1

* Also disables Kempston alias on port DFh

NextREG 132 (84h) – Internal Port Decoding Control 3/4

Group NameRWData BitsDescriptionHD
76543210
Enable AY■■ •Ports FFFDh, BFFDh (AY)1
Enable Soundrive DAC Mode 1■■ • Ports 0Fh,1Fh, 4Fh, 5Fh (DAC SD1)1
Enable Soundrive DAC Mode 2■■ • Ports F1h, F3h, F9h ,FBh (DAC SD2)1
Enable Profi/Covox Stereo DAC■■ • Ports 3Fh, 5Fh (DAC stereo-Profi/Covox)1
Enable Covox Stereo DAC■■ • Ports 0Fh, 4Fh (DAC stereo-Covox)1
Enable Pentagon/ATM DAC■■ • Port FBh (DAC mono-Pentagon) (SD2 off)1
Enable Covox/GS Mono DAC■■ • Port B3h (DAC mono-GS/Covox)1
Enable SPECdrum Mono DAC■■• Port DFh (DAC mono-SPECdrum)*1

* Also a Kempston port 1Fh alias

NextREG 133 (85h) – Internal Port Decoding Control 4/4 (MSB)

Group NameRWData BitsDescriptionHD
76543210
Enable ULAplus■■ •Ports BF3Bh, FF3Bh (ULAplus)■1
Enable DMA■■ • Port 0Bh (Z80DMA)■1
Enable Pentagon 1024 Memory■■ • Port EFF7h (Pentagon 1024 memory)■0
Enable CTC■■ • Ports 183Bh - 1F3Bh (CTC Channels 0-7)■1
Register Reset■■• Register reset mode (soft or hard reset sel.)

NextREG 134 (86h) – Expansion Bus Port Decoding Control 1/4

Group NameRWData BitsDescriptionHD
76543210
Enable Timex■■ •Port FFh■1
Enable Paging■■ • Port 7FFDh■1
Enable Next Memory Paging■■ • Port DFFDh■1
Enable +3 Paging■■ • Port 1FFDh■1
Enable +3 Floating Bus■■ • +3 Floating bus■1
Enable DMA■■ • Port 6Bh (DMA)■1
Enable Kempston Port 1■■ • Port 1Fh (Kempston / MD 1)■1
Enable Kempston Port 2■■• Port 37h (Kempston / MD 2)■1

NextREG 135 (87h) – Expansion Bus Port Decoding Control 2/4

Group NameRWData BitsDescriptionHD
76543210
Enable divMMC■■ •Port E3h (divMMC Control)■1
Enable Multiface■■ • Multiface (two variable ports)■1
Enable I²C■■ • Ports 103Bh, 113Bh (I²C)■1
Enable SPI■■ • Ports E7h, EBh (SPI)■1
Enable UART■■ • Ports 133Bh, 143Bh, 153Bh, 163Bh(UART)■1
Enable Kempston Mouse■■ • Ports FADFh,FBDFh,FFDFh mouse¹■1
Enable Sprites■■ • Ports 57h,5Bh,303Bh (Sprites)■1
Enable Layer 2■■• Port 123Bh (Layer2)■1

1 Also disables Kempston alias on port DFh

NextREG 136 (88h) – Expansion Bus Port Decoding Control 3/4

Group NameRWData BitsDescriptionHD
76543210
Enable AY■■ •Ports FFFDh, BFFDh (AY)■1
Enable DAC Mode 1■■ • Ports 0Fh,1Fh, 4Fh, 5Fh (DAC mode 1)■1
Enable DAC Mode 2■■ • Ports F1h, F3h, F9h ,FBh (DAC mode 2)■1
Enable Profi/Covox Stereo DAC■■ • Ports 3Fh, 5Fh (DAC stereo-Profi/Covox)■1
Enable Covox Stereo DAC■■ • Ports 0Fh, 4Fh (DAC stereo-Covox)■1
Enable Pentagon/ATM DAC■■ • Port FBh (DAC mono Pentagon) (SD2 off)■1
Enable Covox/GS Mono DAC■■ • Port B3h (DAC mono GS/Covox)■1
Enable SPECdrum Mono DAC■■• Port DFh (DAC mono SPECdrum)¹■1

1 Also alias of Kempston port 1Fh

NextREG 137 (89h) – Expansion Bus Port Decoding Control 4/4 (MSB)

Group NameRWData BitsDescriptionHD
76543210
Enable ULAplus■■ •Ports BF3Bh, FF3Bh (ULAplus)■1
Enable DMA■■ • Port 0Bh (Z80DMA)■1
Enable Pentagon 1024 Memory■■ • Port EFF7h (Pentagon 1024 memory)■0
Enable CTC■■ • Ports 183Bh - 1F3Bh (CTC Channels 0-7)■1
Register Reset■■• Register reset mode (soft or hard reset sel.)

The Internal Port Decoding Enables always apply.
When the Expansion Bus is enabled, the Expansion Bus Port Decoding Enables are logically ANDed with the Internal Enables. A result of 0 for the corresponding bit indicates the internal device is disabled. If the Expansion Bus is enabled, this allows I/O cycles for disabled ports to propagate to the Expansion Bus, otherwise corresponding I/O cycles to the Expansion Bus are filtered.

NextREG 138 (8Ah) – Expansion Bus I/O Propagate Control

Group NameRWData BitsDescriptionHD
76543210
Port FEh■■ •Propagate port FEh I/O Cycles■0
Port 7FFDh■■ • Propagate port 7FFDh I/O Cycles■0
Port DFFDh■■ • Propagate port DFFDh I/O Cycles■0
Port 1FFDh■■ • Propagate port 1FFDh I/O Cycles■0
Port FFh■■ • Propagate port FFh I/O Cycles■0
Port EFF7h■■ • Propagate port EFF7h I/O Cycles■0
Reserved■■ 0 0 Reserved, must be 0■0

If any of the bits are set, I/O cycles for the corresponding ports are propagated to the Expansion Bus when the Expansion Bus is enabled. If the internal port decode is still active, any response sent by devices on the Expansion Bus will be ignored
This allows external peripherals to monitor changes in state inside the ZX Spectrum Next. Port FEh is treated specially, so that external keyboards can be attached. When its propagate bit is set, the value read from the bus will be mixed into keyboard reads on port FEh

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[?]

Group NameRW76543210DescriptionHD
AFTER SOFT RESET (Copied into bits D4 through D7)
ROM 0 (128K) Lock Enable■■ •ROM 0 Lock Enable*■0
ROM 1 (48K) Lock Enablen■■ • ROM 1 Lock Enable*■0
ALT ROM Availability Switch■■ • ALT ROM visible ONLY during writes■0
ALT ROM Enable■■ • ALT ROM Enable■0
IMMEDIATE
ROM 0 (128K) Lock Enable■■ • ROM 0 Lock Enable*■0
ROM 1 (48K) Lock Enable■■ • ROM 1 Lock Enable*■0
ALT ROM Availability Switch■■ • ALT ROM visible ONLY during writes■0
ALT ROM Enable■■• ALT ROM Enable■0

* The locking mechanism applies also if the alternative ROM is not enabled. For the +3/+3e and Next personalities if the two lock bits are not 0, then the corresponding ROM page is locked in place. Other personalities (models) use the bits to preferentially lock the corresponding 48K or 128K ROM in place

NextREG 142 (8Eh) – ZX Spectrum 128K Memory Mapping

Group NameRWData BitsDescriptionHD
76543210
RAM bank 0-15■■ ••• Port 7FFDh D2:D0
• Port DFFDh D0
RAM bank in ports 7FFDh, DFFDh paging mode■ 1 Returns 11
■ 0 No change in RAM bank / MMU 6 / MMU 7
1 Change RAM bank
Normal Paging Mode■ 0 Port 1FFDh D0
•Port 7FFDh D4
• Port 1FFDh D2
allRAM Paging Mode■ 1 Port 1FFDh D0
•Port 1FFDh D1
• Port 1FFDh D2

Writes can affect all ports 7FFDh, DFFDh, 1FFDh
Writes always change the ROM / allRAM mapping
Writes immediately change the current MMU mapping as if by Port Write

NextREG 143 (8Fh) – Memory Mapping Mode Control

Group NameRWData BitsDescriptionHD
76543210
Memory Mapping Mode*■■ 00Standard ZX 128K / +3¹■0
01Reserved
10Pentagon 512K²
11Pentagon 1024K³
Reserved■■ 0 0 0 0 0 0 Reserved, must be 0

1 Principally ports 7FFDh, DFFDh and 1FFDh
2 Principally port 7FFDh
3 768 Kb on unexpanded Next machines. Principally ports 7FFDh and EFF7h
* The mapping modes affect how ports 7FFDh, DFFDh, 1FFDh and EFF7h carry out memory paging

NextREG 144 (90h) – PI GPIO Pin Output Enable 1/4

Group NameRWData BitsDescriptionHD
76543210
Pin 0■ •Pin 0 cannot be enabled0
Pin 1■ • Pin 1 cannot be enabled0
Pin 2■■ • Enable0
Pin 3■■ • Enable0
Pin 4■■ • Enable0
Pin 5■■ • Enable0
Pin 6■■ • Enable0
Pin 7■■• Enable0

NextREG 145 (91h) – PI GPIO Pin Output Enable 2/4

Group NameRWData BitsDescriptionHD
76543210
Pin 8■■ •Enable0
Pin 9■■ • Enable0
Pin 10■■ • Enable0
Pin 11■■ • Enable0
Pin 12■■ • Enable0
Pin 13■■ • Enable0
Pin 14■■ • Enable0
Pin 15■■• Enable0

NextREG 146 (92h) – PI GPIO Pin Output Enable 3/4

Group NameRWData BitsDescriptionHD
76543210
Pin 16■■ •Enable0
Pin 17■■ • Enable0
Pin 18■■ • Enable0
Pin 19■■ • Enable0
Pin 20■■ • Enable0
Pin 21■■ • Enable0
Pin 22■■ • Enable0
Pin 23■■• Enable0

NextREG 147 (93h) – PI GPIO Pin Output Enable 4/4 (MSB)

Group NameRWData BitsDescriptionHD
76543210
Pin 24■■ •Enable0
Pin 25■■ • Enable0
Pin 26■■ • Enable0
Pin 27■■ • Enable0

[?]

Group NameRW76543210DescriptionHD
Pin 0■■ •Data1
Pin 1■■ • Data1
Pin 2■■ • Data1
Pin 3■■ • Data1
Pin 4■■ • Data1
Pin 5■■ • Data1
Pin 6■■ • Data1
Pin 7■■• Data1

NextREG 153 (99h) – PI GPIO Pin State 2/4

Group NameRWData BitsDescriptionHD
76543210
Pin 8■■ •Data1
Pin 9■■ • Data0
Pin 10■■ • Data0
Pin 11■■ • Data0
Pin 12■■ • Data0
Pin 13■■ • Data0
Pin 14■■ • Data0
Pin 15■■• Data0

NextREG 154 (9Ah) – PI GPIO Pin State 3/4

Group NameRWData BitsDescriptionHD
76543210
Pin 16■■ •Data0
Pin 17■■ • Data0
Pin 18■■ • Data0
Pin 19■■ • Data0
Pin 20■■ • Data0
Pin 21■■ • Data0
Pin 22■■ • Data0
Pin 23■■• Data0

NextREG 155 (9Bh) – PI GPIO Pin State 4/4 (MSB)

Group NameRWData BitsDescriptionHD
76543210
Pin 24■■ •Data0
Pin 25■■ • Data0
Pin 26■■ • Data0
Pin 27■■ • Data0

Writes to the above registers only propagate to the PI GPIO when the corresponding pin has its output enabled by NextREG 144 (90h) to 147 (93h)

NextREG 160 (A0h) – PI Peripheral Enable

Group NameRWData BitsDescriptionHD
76543210
Enable SPI■■ •Enable SPI on GPIO 7,8,9,10,11 *0
Reserved■■ 0 0 Reserved, must be 0
Enable I2C■■ • Enable I2C on GPIO 2,3 *0
PI Communication Type■■ 0 Connect Rx to GPIO 15, Tx to GPIO 14¹,*0
1 Connect Rx to GPIO 14, Tx to GPIO 15 ²,*
Enable UART³■■ • Enable UART on GPIO 14,15 *0
Reserved■■ 0 0 Reserved, must be 0

* Overrides GPIO Enables
1 For communication with Pi HATS
2 For communication with Pi
3 GPIO 16, 17 will act as RTR_n and CTS_n if the UART is in Hardware Flow Control Mode

NextREG 162 (A2h) – PI I²S Audio Control

Group NameRWData BitsDescriptionHD
76543210
Redirect to EAR■■ •Direct I²S audio to EAR on port 0xFE0
Reserved■■ 1 Reserved, must be 11
Mute R control■■ • Mute right side0
Mute L control■■ • Mute left side0
Audio flow direction■■ 0 PCM_DOUT to Pi, PCM_DIN from Pi (Hats)0
1 PCM_DOUT from Pi, PCM_DIN to Pi (pi)
Reserved■ 0 Reserved, must be 0
I²S state■■00 I²S Disabled*
01 I²S is mono, source R
10 I²S is mono, source L
11 I²S is stereo

* Soft reset sets a default of 00

NextREG 168 (A8h) – ESP WiFi GPIO Output Control

Group NameRWData BitsDescriptionHD
76543210
GPIO 0 Output Control■■ •GPIO 0 Output Enable0
GPIO 2 Output Control■■ 0 GPIO 2 Output Enable¹0

1 Fixed at 0; GPIO 2 is Read-Only

NextREG 169 (A9h) – ESP WiFi GPIO Control

Group NameRWData BitsDescriptionHD
76543210
GPIO 0■■ •Read / Write GPIO 01
GPIO 2■■ • Read / Write GPIO 21
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NextREG 176 (B0h) – Extended Keys 0*

Group NameRWData BitsDescriptionHD
76543210
RIGHT Status■ •Key pressed status flag (1 = pressed)
LEFT Status■ • Key pressed status flag (1 = pressed)
DOWN Status■ • Key pressed status flag (1 = pressed)
UP Status■ • Key pressed status flag (1 = pressed)
. Status■ • Key pressed status flag (1 = pressed)
, Status■ • Key pressed status flag (1 = pressed)
" Status■ • Key pressed status flag (1 = pressed)
; Status■• Key pressed status flag (1 = pressed)

* NextREG 104 (68h) D4 stops extended keys from making entries into the 8x5 keyboard matrix

NextREG 177 (B1h) – Extended Keys 1*

Group NameRWData BitsDescriptionHD
76543210
EXTEND Status■ •Key pressed status flag (1 = pressed)
CAPS LOCK Status■ • Key pressed status flag (1 = pressed)
GRAPH Status■ • Key pressed status flag (1 = pressed)
TRUE VIDEO Status■ • Key pressed status flag (1 = pressed)
INV VIDEO Status■ • Key pressed status flag (1 = pressed)
BREAK Status■ • Key pressed status flag (1 = pressed)
EDIT Status■ • Key pressed status flag (1 = pressed)
DELETE Status■• Key pressed status flag (1 = pressed)

* NextREG 104 (68h) D4 stops extended keys from making entries into the 8x5 keyboard matrix

NextREG 178 (B2h) – Extended MD Pad Buttons

Group NameRWData BitsDescriptionHD
76543210
Left pad MODE Status■ •Button pressed status flag (1 = pressed)
Left pad Y Status■ • Button pressed status flag (1 = pressed)
Left pad Z Status■ • Button pressed status flag (1 = pressed)
Left pad X Status■ • Button pressed status flag (1 = pressed)
Right pad MODE Status■ • Button pressed status flag (1 = pressed)
Right pad Y Status■ • Button pressed status flag (1 = pressed)
Right pad Z Status■ • Button pressed status flag (1 = pressed)
Right pad X Status■• Button pressed status flag (1 = pressed)

NextREG 184 (B8) – divMMC Entry Points 0

Group NameRWData BitsDescriptionHD
76543210
0000h Automap Control■■ •1 to enable automap (instruction fetch)1
0008h Automap Control■■ • 1 to enable automap (instruction fetch)1
0010h Automap Control■■ • 1 to enable automap (instruction fetch)
0018h Automap Control■■ • 1 to enable automap (instruction fetch)
0020h Automap Control■■ • 1 to enable automap (instruction fetch)
0028h Automap Control■■ • 1 to enable automap (instruction fetch)
0030h Automap Control■■ • 1 to enable automap (instruction fetch)
0038h Automap Control■■• 1 to enable automap (instruction fetch)1

NextREG 185 (B9h) – divMMC Entry Points Valid 0

Group NameRWData BitsDescriptionHD
76543210
Entry point at 0000h■■ •1 for always*1
Entry point at 0008h■■ • 1 for always*0
Entry point at 0010h■■ • 1 for always*0
Entry point at 0018h■■ • 1 for always*0
Entry point at 0020h■■ • 1 for always*0
Entry point at 0028h■■ • 1 for always*0
Entry point at 0030h■■ • 1 for always*0
Entry point at 0038h■■• 1 for always*0

* Otherwise when ROM3 is present

NextREG 186 (BAh) – divMMC Entry Points Timing Control 0

Group NameRWData BitsDescriptionHD
76543210
Entry point at 0000h■■ •1 for instant mapping otherwise delayed0
Entry point at 0008h■■ • 1 for instant mapping otherwise delayed0
Entry point at 0010h■■ • 1 for instant mapping otherwise delayed0
Entry point at 0018h■■ • 1 for instant mapping otherwise delayed0
Entry point at 0020h■■ • 1 for instant mapping otherwise delayed0
Entry point at 0028h■■ • 1 for instant mapping otherwise delayed0
Entry point at 0030h■■ • 1 for instant mapping otherwise delayed0
Entry point at 0038h■■• 1 for instant mapping otherwise delayed0

NextREG 187 (BBh) – divMMC Entry Points 1

Group NameRWData BitsDescriptionHD
76543210
Entry point at 0066h (delayed)■■ •1 to enable automap (instr. fetch + button)1
Entry point at 0066h (instant)■■ • 1 to enable automap (instr. fetch + button)0
Entry point at 04C6h (ROM3)¹■■ • 1 to enable automap (instr. fetch/delayed)1
Entry point at 0562h (ROM3)¹■■ • 1 to enable automap (instr. fetch/delayed)1
Entry point at 04D7h (ROM3)²■■ • 1 to enable automap (instr. fetch/delayed)0
Entry point at 056Ah (ROM3)²■■ • 1 to enable automap (instr. fetch/delayed)0
Entry points at 1FF8h:1FFFh■■ • 1 to disable automap (instr. fetch/delayed)1
Entry points at 3Dxxh (ROM3)³■■• 1 to enable automap (instr. fetch/instant)1

1 Tape traps. Original divMMC + esxDOS
2 Tape traps. NextZXOS (these offer better compatibility with tape-based software)
3 Used by TR-DOS

INTERRUPTS

NextREG 192 (C0h) – Interrupt Control

Group NameRWData BitsDescriptionHD
76543210
Maskable Interrupt Mode■■ 0Pulse0
Current Z80 Interrupt Mode■ 00 Interrupt Mode 00
01 Interrupt Mode 1
10 Interrupt Mode 2
Stackless NMI Enable¹■■ • Toggle (1=enable, 0=disable)0
Reserved■■ 0 Reserved, must be 00
IM2 vector■■••• Programmable portion of IM2 vector0
Maskable Interrupt Mode■■ 1Hardware IM2²0
Interrupt Vector Generated■■ .0000 Line interrupt (Highest Priority)
0001 UART 0 Rx
0010 UART 1 Rx
0011 CTC Channel 0
0100 CTC Channel 1
0101 CTC Channel 2
0110 CTC Channel 3
0111 CTC Channel 4
1000 CTC Channel 5
1001 CTC Channel 6
1010 CTC Channel 7
1011 ULA
1100 UART 0 Tx
1101 UART 1 Tx (lowest priority)
••• NextREG 192 (C0h) D7:D5

1 The return address pushed during an NMI acknowledge cycle will be written to NextREG instead of memory (the SP will be decremented) and the first RETN after the acknowledge will take its return address from NextREG instead of memory (the SP will be incremented)
If D3 = 0 and in other circumstances (see advanced hardware manual), RETN functions normally
2 In Hardware IM2 Mode the expansion bus is the lowest priority interrupter and if no vector is supplied externally then 255 (FFh) will be generated

NextREG 194 (C2h) – NMI Return Address LSB

Group NameRWData BitsDescriptionHD
76543210
NMI Return Address■■••••••••8-bit value (LSB)*

The return address written during an NMI acknowledge cycle is always stored in this and the next (NextREG C3h) registers

NextREG 195 (C3h) – NMI Return Address MSB

Group NameRWData BitsDescriptionHD
76543210
NMI Return Address■■••••••••8-bit value (MSB)*

The return address written during an NMI acknowledge cycle is always stored in this and the previous (NextREG C2h) registers

NextREG 196 (C4h) – Interrupt Enables 0

Group NameRWData BitsDescriptionHD
76543210
ULA■■ •1 to enable*1
Line■■ • 1 to enable*0
Reserved■■ 0 0 0 0 0 Reserved must be 00
Expasion Bus I̅N̅T̅■■• 1 to enable1

* Aliases of interrupt enable bits in NextREG 34 (22h)
If a device interrupt is disabled, it enters a polled mode

NextREG 197 (C5h) – Interrupt Enables 1

Group NameRWData BitsDescriptionHD
76543210
CTC Channel 0 ZC/TO■■ •1 to enable0
CTC Channel 1 ZC/TO■■ • 1 to enable0
CTC Channel 2 ZC/TO■■ • 1 to enable0
CTC Channel 3 ZC/TO■■ • 1 to enable0
CTC Channel 4 ZC/TO■■ • 1 to enable0
CTC Channel 5 ZC/TO■■ • 1 to enable0
CTC Channel 6 ZC/TO■■ • 1 to enable0
CTC Channel 7 ZC/TO■■• 1 to enable0

If a device interrupt is disabled, it enters a polled mode

NextREG 198 (C6h) – Interrupt Enables 2

Group NameRWData BitsDescriptionHD
76543210
UART 0 Rx available¹■■ •1 to enable0
UART 0 Rx near-full¹■■ • 1 to enable0
UART 0 Tx empty■■ • 1 to enable0
Reserved■■ 0 Reserved, must be 00
UART 1 Rx available²■■ • 1 to enable0
UART 1 Rx near-full²■■ • 1 to enable0
UART 1 Tx empty■■ • 1 to enable0
Reserved■■ 0 Reserved, must be 00

1 Shared interrupt. Rx near-full overrides Rx available
2 Shared interrupt. Rx near-full overrides Rx available
If a device interrupt is disabled, it enters a polled mode

NextREG 199 (C7h) – Reserved

Group NameRWData BitsDescriptionHD
76543210
Reserved, write 0■■ 0 0 0 0 0 0 0 0Reserved, must be 00
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[?]

[?]RW76543210DescriptionHD
[?]■■ •Status
[?]■■ • Status
[?]■■ 0 0 0 0 0 0 Reserved must be 0

[?]g, set bits indicate that the device generated an interrupt in the past or an in-
[?]nding
[?], set bits clear the status. In Hardware IM2 mode, the status will continue be-
[?]set until the interrupt pending condition is cleared

[?]C9h) – Interrupt Status 1

[?]RWData BitsDescriptionHD
76543210
[?]■■ •Status
[?]■■ • Status
[?]■■ • Status
[?]■■ • Status
[?]■■ • Status
[?]■■ • Status
[?]■■ • Status
[?]■■• Status

[?]g, set bits indicate that the device generated an interrupt in the past or an in-
[?]nding
[?], set bits clear the status. In Hardware IM2 mode, the status will continue be-
[?]set until the interrupt pending condition is cleared

[?]CAh) – Interrupt Status 2

[?]RWData BitsDescriptionHD
76543210
[?]■■ •Status0
[?]■■ • Status0
[?]■■ • Status0
[?]■■ 0 Reserved, must be 00
[?]■■ • Status0
[?]■■ • Status0
[?]■■ • Status0
[?]■■ 0 Reserved, must be 00

[?]upt
[?]upt
[?]g, set bits indicate that the device generated an interrupt in the past or an in-
[?]nding
[?], set bits clear the status. In Hardware IM2 mode, the status will continue be-
[?]set until the interrupt pending condition is cleared

[?]CBh) – Reserved

[?]RWData BitsDescriptionHD
76543210
[?]■■ 1 1 1 1 1 1 1 Reserved, must be 1

[?]Fh)

[?]CCh) – DMA Interrupt Enables 0

[?]RWData BitsDescriptionHD
76543210
[?]■■ •1 to enable0
[?]■■ • 1 to enable0
[?]■■• 1 to enable0

[?]ate the corresponding interrupt will interrupt a DMA operation when in Hard-
[?]ode

[?]CDh) – DMA Interrupt Enables 1

[?]RWData BitsDescriptionHD
76543210
[?]■■ •1 to enable0
[?]■■ • 1 to enable0
[?]■■ • 1 to enable0
[?]■■ • 1 to enable0
[?]■■ • 1 to enable0
[?]■■ • 1 to enable0
[?]■■ • 1 to enable0
[?]■■• 1 to enable0

[?]ate the corresponding interrupt will interrupt a DMA operation when in Hard-
[?]ode

[?]CEh) – DMA Interrupt Enables 2

[?]RWData BitsDescriptionHD
76543210
[?]■■ •1 to enable0
[?]■■ • 1 to enable0
[?]■■ • 1 to enable0
[?]■■ 0 Reserved, must be 00
[?]■■ • 1 to enable0
[?]■■ • 1 to enable0
[?]■■ • 1 to enable0
[?]■■ 0 Reserved, must be 00

[?]ate the corresponding interrupt will interrupt a DMA operation when in Hard-
[?]ode

[?]

Group NameRW76543210DescriptionHD
Reserved, write 0■■ 0 0 0 0 0 0 0 0Reserved, must be 0

* Write 0 (00h)

Since interrupts are only sampled at the end of an instruction by the Z80N, each time the DMA is interrupted, one instrucion of progress is made in the main program

NextREG 216 (D8h) – I/O Traps (Experimental)

Group NameRWData BitsDescriptionHD
76543210
+3 FDC■■ •1 to enable on ports 2FFDh and 3FFDh0
Reserved■■ 0 0 0 0 0 0 0 Reserved, must be 0

* An I/O trap generates a Multiface NMI and is indicated in NextREG 2 (02h)
Traps cannot be triggered by the DMA or while the Multiface, divMMC or external NMI is active

NextREG 217 (D9h) – I/O Traps Write (Experimental)

Group NameRWData BitsDescriptionHD
76543210
Data■■••••••••8-bit value

Holds data written during trapped I/O write cycle

NextREG 218 (DAh) – I/O Trap Cause (Experimental)

Group NameRWData BitsDescriptionHD
76543210
I/O Trap Cause■■ 00None – 0 at the time NR 02 (02h) D4 is 0
01Port 2FFDh read
10Port 3FFDh read
11Port 3FFDh write

* If NextREG 02 (02h):D4 indicates that an I/O cycle was trapped, this register indicates the cause

NextREG 240 (F0h) – XDEV (Issue 4 ZX Spectrum Next Only)

Group NameRWData BitsDescriptionHD
76543210
Select Mode*■1 Select Mode Enabled1
Currently Selected Device■ 00none
01Xilinx™ DNA (See below)
10Xilinx™ XADC (See below)
Select Device*■1 Enter Select Mode
0 Enter Selected Device Mode
1 Change Selected Device
No Device Selected■ 00none
DNA ■ • DNA bit (serial stream shifts left)¹
SELECT / DNA RELOAD ■ 1 Enter Select Mode or DNA string reload
BUSY ■ 1 1 if XADC busy with conversion
EOC ■ 1 1 if XADC conv. complete since last read²
EOS ■ 1 1 if XADC conv. seq. comp. since last read²
SELECT ■ 1 Enter Select Mode
XADC RESET ■ 1 1 to reset XADC
XADC CONVST ■ 1 1 to start conversion

* Re-enter Select Mode at any time by writing to the register with D7 set
Select a device to communicate with by writing to the register with D7:D6 set then exit Select Mode by clearing D7. Thereafter the particular device is attached to the NextREG
1 The first eight bits read will indicate the length of the following DNA bits
2 Read clears

NextREG 248 (F8h) – XADC Register* (Issue 4 ZX Spectrum Next Only)

Group NameRWData BitsDescriptionHD
76543210
DADDR■■ •••••••XADC DRP register address value■0
XADC DRP port read/write mode**■■0 Initiate read from XADC DRP port
1Initiate write to XADC DRP port

* An XADC Register read or write is initiated by writing to this register
Before initiating a write, store the value in NextREG 249 (F9h) and NextREG 250 (FAh) first
There must be at least six 28 MHz cycles after each read or write initiation before the action is completed
** Reads as 0

NextREG 249 (F9h) – XADC D0 (Issue 4 ZX Spectrum Next Only)

Group NameRWData BitsDescriptionHD
76543210
DRP Data Bus LSB (D7:D0)■■••••••••Data■0

* DRP reads store result here and DRP writes take value from here

NextREG 250 (FAh) – XADC D1 (Issue 4 ZX Spectrum Next Only)

Group NameRWData BitsDescriptionHD
76543210
DRP Data Bus MSB (D15:D8)■■••••••••Data■0

* DRP reads store result here and DRP writes take value from here

NextREG 255 (FFh) - Reserved (Internal Use Only)

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Other port addresses

As seen in the table at the beginning of this chapter and the discussion about decoding, all even addresses refer to ULA functions. You may find yourself in need to read the keyboard directly from the hardware. As mentioned, part of the ULA's function is to return the state of keypresses. The keyboard is divided in 8 half-rows of 5 keys each, each half-row having its own port address5.

Address
Decimal / Hex		BitsAddress
Decimal / Hex
D0D1D2D3D4D4D3D2D1D0
63486 / F7FEh123456789061438 / EFFEh
64510 / FBFEhQWERTYUIOP57342 / DFFEh
65022 / FDFEhASDFGHJKLEnter49150 / BFFEh
65278 / FEFEhCapsZXCVBNMSymSpace32766 / 7FFEh

The diagram above neatly illustrates how the keyboard matrix is separated into half-rows (demarcated by the thick line in the middle). Pay attention to how bits are mirrored going from the outside of the keyboard to the inside.

The address of each half-row in the diagram is calculated as: 254 + 256*(255 - 2ⁿ).

In the formula above, n is the number of half-row which starts with 0 at the bottom right and moves in a counterclockwise manner with each successive half-row increasing by 1.

In the byte read in, bits D0 to D4 stand for each of the five keys in the given half-row – D0 for the outside key and D4 for the one nearest the middle. The bit is 0 if the key is pressed and 1 if it is not.

For example to find the value of the CAPS SHIFT key, you can do:

PRINT %IN 65278 & @1

Writing a value using OUT to the ULA (Port 254 / FEh) controls other hardware as well. You can drive the beeper with D4, the MIC socket with D3, read the EAR socket with D6 and modify the BORDER colour using bits D0,D1 and D2. For example to make the border a nice magenta colour you can:

OUT 254, %@00000011

Port addresses 32765 (7FFDh), 8189 (1FFDh) and 57341 (DFFDh) control the extra memory. Executing an OUT to these ports from NextBASIC without knowing the ramifications will nearly always cause the computer to crash, losing any program and data. These ports are write-only, i.e. you cannot determine the current state of the paging by an IN instruction. This is why the BANKM system variable is always kept up to date with the last value output to this port. Check the last section in this chapter as well as Chapter 23 – The Memory where we examine the banking system in detail.

Writing to port 65533 (FFFDh) will select a particular PSG register (on the AY sound chip) and writing to port 49149 (BFFDh) will send a particular value to that register. Reading from port 65533 (FFFDh) returns the value stored in the selected register. Judicious use of these two registers can allow sounds to be generated while NextBASIC gets on with something else.

The section that follows describes all ZX Spectrum Next – specific hardware ports; addressing them is via OUT and IN commands.

5 Extended keys are combinations of tther keys, so they need to be read as those key combinations. For example EXTEND is CAPS SHIFT + SYMBOL SHIFT.

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The ZX Spectrum Next Hardware Ports List

NOTE

The following Hardware Ports are not listed:
ULA 254 (FEh), Legacy Memory Paging 3765 (7FFDh), 8189 (1FFDh), 57341 (DFFDh), 61431 (EFF7h), Layer 2 4667 (123Bh) and ULAplus 65339 (FF3Bh) / 48955 (BF3B)
Ports are arranged according to their function.
Please also consult the ports.txt document found in your System/Next™ distribution for a complete list of ports

Input / Output / Legacy Video

Port 255 (FFh) – Timex SCLD ULA Extensions*

Group NameRWData BitsDescription
76543210
Screen Mode Select■■000Std: DFILE0+COLOURFILE0 @ 4000h
001Shd: DFILE1+COLOURFILE1 @ 6000h
010HC: DFILE @ 4000h, COLOURFILE @ 6000h
110HR: even DFILE @ 4000h, odd DFILE @6000h
HiRes Colour Scheme Select■■000BRIGHT Black on White
001BRIGHT Blue on Yellow
010BRIGHT Red on Cyan
011BRIGHT Magenta on Green
100BRIGHT Green on Magenta
101BRIGHT Cyan on Red
110BRIGHT Yellow on Blue
111BRIGHT White on Black
Frame Interrrupt Control■■•1 to Disable ULA Frame Interrupt
Timex MMU Select¹■■•Timex Horizontal MMU Bank Select

* Only readable if NR 8 (08h):D2 = 1
¹ Not implemented on the ZX Spectrum Next

Port 64479 (FBDFh) – Kempston Mouse X position

Group NameRWData BitsDescription
76543210
Current X Position■••••••••Value 0 – 255*

* Returns the current X position of the mouse 0 - 255.
The value wraps from 255 to 0 on a right movement and from 0 to 255 on a left movement.

Port 65503 (FFDFh) – Kempston Mouse Y position

Group NameRWData BitsDescription
76543210
Current Y Position■••••••••Value 0 - 255*

* Returns the current Y position of the mouse 0 - 255.
The value decrements and wraps from 255 to 0 on a downward movement and increments and wraps from 0 to 255 on an upward movement.

Port 64223 (FADFh) – Kempston Mouse Button Status

Group NameRWData BitsDescription
76543210
Mouse Button Flags¹■•Left Mouse button status
•Right Mouse button status
•Middle Mouse button status
Mouse Wheel Position²■••••Mouse Wheel position (Wraps)

¹ Pressed = 1, Not Pressed = 0
² Value 0 to 15. Upwards scroll 15 to 0 – wraps to 15; Downards scroll 0 to 15 – wraps to 0

Port 31 (1Fh) – Kempston Joystick 1 / Mega Drive Pad 1 Status

Group NameRWData BitsDescription
76543210
Joystick Movement Status■•Right (pin 4)
•Left (pin 3)
•Down (pin 2)
•Up (pin 1)
Joystick Button Status■•Fire 1 (MD = B) (pin 6)
•Fire 2 (MD = C) (pin 9)
•MD = A (0 on Kempston)
•MD Start (0 on Kempston)

Joystick ports can be placed in I/O mode via NR 11 (0Bh)
Kempston joysticks and Mega Drive Pads share ports but MD pads use more bits
The X/Y/Z buttons on MD pads can be read via NR 178 (B2h)
All twelve MD pad buttons can be assigned to the keyboard – See NR 05 (05h)
When using an MD pad in more limited joystick modes, the excess buttons can generate keypresses if so programmed

Port 55 (37h) – Kempston Joystick 2 / Mega Drive Pad 2 Status

Group NameRWData BitsDescription
76543210
Joystick Movement Status■•Right (pin 4)
•Left (pin 3)
•Down (pin 2)
•Up (pin 1)
Joystick Button Status■•Fire 1 (MD = B) (pin 6)
•Fire 2 (MD = C) (pin 9)
•MD = A (0 on Kempston)
•MD Start (0 on Kempston)

Joystick ports can be placed in I/O mode via NR 11 (0Bh)
Kempston joysticks and Mega Drive Pads share ports but MD pads use more bits
The X/Y/Z buttons on MD pads can be read via NR 178 (B2h)
All twelve MD pad buttons can be assigned to the keyboard – See NR 05 (05h)
When using an MD pad in more limited joystick modes, the excess buttons can generate keypresses if so programmed

Audio

Port 65533 (FFFDh) – PSG Control and Register Select

Group NameRWData BitsDescription
76543210
Selected Register Status■••••••••Value in selected register of active PSG
Active PSG Control■00Reserved
11PSG 0 made active*
10PSG 1 made active
01PSG 2 made active
Stereo Channel Control¹■1Reserved, must be 1
1Reserved, must be 1
1Reserved, must be 1
•Right Channel Enable
•Left Channel Enable
1Reserved, must be 1
Register Select²••••If 0000 selects a register from the Active PSG

* Default value
¹ If NR 8 (08h):D1 = 1 and D7 through D4 are not 0000

Port 49149 (BFFDh) – PSG Data

Group NameRWData BitsDescription
76543210
Selected Register Status¹■••••••••Value in selected register of active PSG
Active PSG Register Data■••••••••Value to write to the register

¹ Readable if machine type is ZX Spectrum Next or ZX Spectrum +3 only.

Port 49141 (BFF5h) – PSG Info

Group NameRWData BitsDescription
76543210
Currently selected PSG register■•••••Value of selected register of active PSG
Reserved■•Reserved
Active PSG■11PSG 0 is active
10PSG 1 is active
01PSG 2 is active

Ports 251¹, 223², 31³, 241⁴, 63⁵ (FBh, DFh, 1Fh, F1h, 3Fh) – DAC Channel A (Left)

Group NameRWData BitsDescription
76543210
DAC output■••••••••8-bit unsigned sample value

All DACs originate from various ZX Spectrum peripherals and compatible models and are kept for compatibility. DACs are enabled by setting NR 8 (08h):D3 = 1
¹ Found in Pentagon and ATM
² Found in SpecDRUM™
³ Found in SoundDrive 1
⁴ Found in SoundDrive 2
⁵ Found in Profi Covox

Ports 179¹, 15², 243³ (B3h, 0Fh, F3h) – DAC Channel B (Left)

Group NameRWData BitsDescription
76543210
DAC output■••••••••8-bit unsigned sample value

All DACs originate from various ZX Spectrum peripherals and compatible models and are kept for compatibility. DACs are enabled by setting NR 8 (08h):D3 = 1
¹ Found in GS Govox
² Found in SoundDrive 1 and Covox
³ Found in SoundDrive 2

Ports 179¹, 79², 249³ (B3h, 4Fh, F9h) – DAC Channel C (Right)

Group NameRWData BitsDescription
76543210
DAC output■••••••••8-bit unsigned sample value

All DACs originate from various ZX Spectrum peripherals and compatible models and are kept for compatibility. DACs are enabled by setting NR 8 (08h):D3 = 1
¹ Found in GS Govox
² Found in SoundDrive 1 and Covox
³ Found in SoundDrive 2

Ports 251¹, 223², 95³ (FBh, DFh, 5Fh) – DAC Channel D (Right)

Group NameRWData BitsDescription
76543210
DAC output■••••••••8-bit unsigned sample value

All DACs originate from various ZX Spectrum peripherals and compatible models and are kept for compatibility. DACs are enabled by setting NR 8 (08h):D3 = 1
¹ Found in Pentagon, ATM and SoundDrive 2
² Found in SpecDRUM™
³ Found in SoundDrive 1 and Profi Covox

Storage

Port 227 (E3h) – divMMC Control

Group NameRWData BitsDescription
76543210
RAM bank Control■■••••Memory Bank Select for 8K - 16K region
MapRAM Control¹■■•MapRAM Enable
ConMEM Control²■■•ConMEM Enable

¹ Can only be set once. On the original divMMC only a power cycle can reset it. The ZX Spectrum Next implementation uses NR 9 (09h) where D3 can be set,in order to reset this bit. When set, it replaces the expected esxDOS ROM with divMMC RAM bank 3
² Can be used to manually control divMMC mapping. When set it maps in divMMC; 0K - 8K will contain the esxDOS ROM, 8K - 16K will contain the selected divMMC bank (from D0 through D3). The divMMC automatically maps itself in when instruction fetches hit specific addresses in the ROM. When this happens, the esxDOS ROM (or divMMC bank 3 if mapRAM is set) appears in 0K - 8K and the selected divMMC bank appears as RAM in 8K - 16K. DivMMC automapping is normally disabled by NextZXOS. See NR 6 (06h):D4. The divMMC has been enhanced, in order to add entry points and make them programmable.

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Communication

Port 4155 (103Bh) – I²C SCL

Group NameRWData BitsDescription
76543210
I²C Clock Line Control■■•State of the Clock Line

Port 4411 (113Bh) – I²C SDA

Group NameRWData BitsDescription
76543210
I²C Data Line Control■■•State of the Data Line

Port 231 (E7h) – SPI CS*

Group NameRWData BitsDescription
76543210
SD Card 0 Select■■•Select SD Card 0
SD Card 1 Select■■•Select SD Card 1
PI SPI 0 Select¹■■•Select Pi SPI 0 on the GPIO pins
PI SPI 1 Select¹■■•Select Pi SPI 1 on the GPIO pins
FPGA Flash Select■■•Select the FPGA Flash ROM (Internal Use Only)

* The SPI port's data lines are active low (0 to select).
¹ Pi GPIO must be configured for SPI. See NR 160 (A0h)
Five devices are connected to the SPI interface. The ZX Spectrum Next must be
SPI master.
Only one of D0 through D3 can be 0 at one time. If not, the result will be no device selected

Port 235 (EBh) – SPI Data

Group NameRWData BitsDescription
76543210
SPI Data■■••••••••Read/Write data to the selected SPI device

Port 5435 (153Bh) – UART Control

Group NameRWData BitsDescription
76543210
Prescalar MSB Value■■•••Baud rate prescalar MSB
Prescalar MSB Write Enable■■•D2:D0 write enable
UART Select**■■0ESP UART Select
1Pi0 UART Select*

* Pi GPIO must be configured for UART. See NR 160 (A0h)
** Either UART can be redirected to the joystick ports, see NR 11 (0Bh)

Port 4923 (133Bh) – UART Transmit

Group NameRWData BitsDescription
76543210
Read buffer status flag■•Set if read buffer contains received bytes
Transmitter busy flag■•Set if the transmit buffer is full
Read buffer full flag■•Set if the read buffer overflowed*
Read buffer near-full flag■•Set if the read buffer in near-full (¾)
Transmit buffer empty flag■•Set if the transmit buffer is empty
Receive data after error flag■•Set if the next Rx byte was recv'd after an error**
Receive framing error flag■•Set if the Rx experienced a framing error***
Receive in break flag■•Set if the Rx is in a break condition****
Data Transmit■••••••••Send a byte to the connected device

* Clears on read
** Framing or overflow
*** Clears on read; includes parity and stop bit errors
**** External device has held Tx=0 for at least 20 bit periods
Both UARTs have a 64-byte transmit buffer

Port 5179 (143Bh) – UART Receive

Group NameRWData BitsDescription
76543210
Data Receive■••••••••Reads a byte from the receive buffer*
Prescalar LSB Value¹■0•••••••Lower 7 bits of the 14-bit prescalar value LSB
1•••••••Upper 7 bits of the 14-bit prescalar value LSB

* If the buffer is empty 0 is returned.
¹ The UART's baud rate is determined by the prescalar according to this formula:
Prescalar = Fsys / baudrate; Fsys = System Clock from NR 17 (11h).
Example: If the system is on a Digital display, NR 17 (11h) indicates that Fsys = 27000000.
The prescalar for a baud rate of 115200 is 27000000 / 115200 = 234
Both UARTs have a 512-byte receive buffer

Port 5691 (163Bh) – UART Frame

Group NameRWData BitsDescription
76543210
Stop bits control■■•Set if 2 stop bits, clear for 1 stop bit
Parity type control■■•Set if odd parity, clear for even parity
Parity check control■■•Set to enable parity check
Frame size (bits) control■■005 bits
016 bits
107 bits
118 bits
Hardware Flow control■■•Set enables hardware flow control*
Transmit break control**■■•Send a byte to the connected device
Reset Rx and Tx Control■■•Set to immediately reset Rx, Tx and empty FIFOs

* Honoured only on an Issue 4 ESP module, no effect on Issue 2 boards. In joystick I/O mode only CTS is available
** Asserts break on Tx when Tx becomes idle

Sprites

Port 12347 (303Bh) – Sprite Slot Select*¹

Group NameRWData BitsDescription
76543210
Sprite Collision flag■•Set if any two displayed sprites collide on screen
Max. No. of Sprites per line flag■•Set if maximum no. of sprites per line exceeded
Current Pattern Index Select²■•••••••Sets Current Pattern Index
Current Sprite Index Select¹■•••••••Sets Current Sprite (0 - 127)

* Reading the port clears all flags
¹ The current sprite and pattern index are separate quantities internally
² The pattern index is 6-bit in bits D0 through D5 and selects pattern 0 - 63 in the pattern RAM. Each pattern is 256 bytes long. D7 can be used to offset 128 bytes halfway through the pattern; this accommodates 4-bit sprites whose patterns are 128 bytes in size.

Port (57h) – Sprite Attributes

Group NameRWData BitsDescription
76543210
Attribute Data■••••••••Attribute Data

Writes the current sprite's attributes. Each sprite has either 4 or 5 attributes and after all are written, the current sprite pointer is advanced to the next sprite. The pointer wraps from 127 to 0.

Port (5Bh) – Sprite Pattern

Group NameRWData BitsDescription
76543210
Pattern Data■••••••••Pattern Data

Writes a byte to the current pattern address and advances the current address by one. The pattern address is changed by writing the pattern index in port 12347 (303Bh). A pattern index indicates the start of a 256-byte range of data used to define an 8-bit sprite pattern or a 128-byte range of data use to define a 4-bit sprite pattern.

DMA

Port 107 (6Bh) / 11 (0Bh) – zxnDMA / Z80DMA

Group NameRWData BitsDescription
76543210
DMA Control■■••••••••DMA command value

The zxnDMA implements a subset of the Zilog Z80DMA architecture while adding a burst mode primarily used to play digital music. Accessing the DMA via port 11 (0Bh) rather than 107 (6Bh) selects the DMA compatibility mode (Z80DMA). See https://www.specnext.com/the-zxndma/

Layer 2 Graphics

Port 4667 (123Bh) – Layer 2 Control

Group NameRWData BitsDescription
76543210
Memory Write Mapping Control■■•Enable Mapping for Memory Writes
Layer 2 Display Control■■•Enable Layer 2 Display
Memory Read Mapping Control■■•Enable Mapping for Memory Reads
Active/Shadow Control■■0Map Active Layer 2¹
1Map Shadow Layer 2²
Reserved■00Reserved, Must be 0
Layer 2 Map Type Select■■00First 16K of Layer 2 in the bottom 16K
01Second 16K of Layer 2 in the bottom 16K
10Third 16K of Layer 2 in the bottom 16K
11First 48K of Layer 2 in the bottom 48K

* Memory pointed at by NR 18 (12h) or NR 19 (13 h) can be mapped into the lower 16K or 48K if Layer 2 memory mapping is enabled in D2 and/or D0. This mechanism is separate from MMU and will overlay the paging state set by MMU but only if the memory access type matches the enable condition (Read-only, Write-only)
¹ See NR 18 (12h)
² See NR 19 (13h)

Memory Mapping Modes

The current memory mapping is maintained by the hardware in eight MMUs with each MMU, numbered MMU0 – MMU7, holding an 8K page number currently mapped into corresponding eight 8K slots of the Z80's 64K memory space. The individual MMUs can be programmed via NextREGs 80 – 87 (50h – 57h).

The traditional banking mechanism used in various Spectrum models is via ports 7FFDh, DFFDh, 1FFDh and EFF7h with writes to these ports making changes to one or more MMUs in the hardware.

The 128K Spectrum used port 7FFDh, the +3 used 7FFDh and 1FFDh and the ZX Spectrum Next extends that with port DFFDh to increase the range of 16K banks that can be paged into the top 16K.

Russian ZX Spectrum models extended the banking in various ways to support up to 1MB of memory. The ZX Spectrum Next, also supports some of these banking methods which modify the behaviour of ports 7FFDh and DFFDh. The current memory mapping mode is held in NextREG 143 (8Fh) and can be one of standard ZX Spectrum, Pentagon 512K or Pentagon 1024K. The ZX Spectrum Next normally operates in standard Spectrum mode.

In standard spectrum mode, ports 7FFDh and 1FFDh operate as on the +3 and as described above.

Port DFFDh adds four bits to extend the three bit bank number in bits D2:D0 of port 7FFDh so that the full range of the ZX Spectrum

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Next's memory can be paged into the top 16K.

Also in this mode, D3 of port EFF7h can be set to place 16K bank 0 into the bottom 16K, overlaying the ROM.

Writes to ports 7FFDh, DFFDh, 1FFDh and EFF7h, will cause the bottom 16K and the top 16K to remap; if allRAM mode is selected, the entire 64K remaps.

In Pentagon 512K mode, port 7FFDh is extended so that bits D7:D6 augment the bank number in bits D2:D0 to form a 5-bit bank number for the top 16K.

On the ZX Spectrum Next, port 1FFDh continues to function (allRAM mode and ROM selection) and D3 of port EFF7h can be set to map 16K bank 0 on top of ROM in the bottom 16K.

Writes to ports 7FFDh, DFFDh, 1FFDh and EFF7h will cause the bottom 16K and the top 16K to remap; if allRAM mode is selected, the entire 64K remaps.

In Pentagon 1024K mode, port EFF7h D2 = 0 enables Pentagon 1024K mapping and port EFF7h D2 = 1 selects standard ZX Spectrum mapping as described above.

With Pentagon 1024K mode active, port 7FFDh is unlocked and D5 (the lock bit) is repurposed as another bank bit.

The bank number paged into the top 16K is taken as port 7FFDh bits {D5,D7,D6,D2,D1,D0} to reach 1MB in 16K banks.

On the Next, port 1FFDh continues to function (allRAM mode and ROM selection) and D3 of port EFF7h can be set to map 16K bank 0 on top of ROM in the bottom 16K.

Writes to ports 7FFDh, DFFDh, 1FFDh and EFF7h will cause the bottom 16K and the top 16K to remap; if allRAM mode is selected, the entire 64k remaps.

For 100% compatibility with the original banking methods listed above, extra ports like 1FFDh can be disabled using the internal port decodes with NextREGs 130 - 133 (82h - 85h).

The Expansion Bus

The Expansion Bus is found in the back of the ZX Spectrum Next and exposes its CPU to the world. As it too gets addressed by IN and OUT commands, it is listed below:

Bottom SideA112828ReservedTop Side
A92727A10
B̅U̅S̅A̅C̅K̅2626A8
R̅O̅M̅C̅S̅2525R̅F̅S̅H̅
A42424M̅1̅
A52323NC
A62222NC
A72121W̅A̅I̅T̅
R̅E̅S̅E̅T̅2020NC
BUSREQ61919W̅R̅
NC1818R̅D̅
NC1717I̅O̅R̅Q̅
Reserved1616M̅R̅E̅Q̅
R̅O̅M̅C̅S̅1515H̅A̅L̅T̅
GND1414N̅M̅I̅
I̅O̅R̅Q̅U̅L̅A̅1313I̅N̅T̅
A31212D4
A21111D3
A11010D5
A099D6
C̅L̅K̅88D2
GND77D1
GND66D0
Key55Key
+9V (PSU)744R̅O̅M̅C̅S̅
+5V33D7
A1222A13
A1411A15

The ZX Spectrum Next Expansion Bus

6 BUSREQ is incorrectly active High oin Issue 2 but fixed on Issue 4 7: This pin receives the unregulated power from the PSU line. If you plug a higher voltage PSU, that voltage will be present at that pin and may damage your peripherals

← Chapter 21 – Optional FeaturesChapter 23 – The Memory →

ZX Spectrum Next User Manual, 3rd Edition (ISBN 978-1-5272-5496-1), written and illustrated by Phoebus R. Dokos. Copyright © 2020-2024 Phoebus Dokos / SpecNext Ltd. Licensed under CC BY-NC-SA 4.0. This is a transcription and can contain errors; check any doubt against the printed page.