| Group Name | R | W | Data Bits | Description | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||||
| I²C Clock Line Control | ■ | ■ | • | State of the Clock Line | |||||||
| Group Name | R | W | Data Bits | Description | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||||
| I²C Data Line Control | ■ | ■ | • | State of the Data Line | |||||||
| Group Name | R | W | Data Bits | Description | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||||
| SD Card 0 Select | ■ | ■ | • | Select SD Card 0 | |||||||
| SD Card 1 Select | ■ | ■ | • | Select SD Card 1 | |||||||
| PI SPI 0 Select¹ | ■ | ■ | • | Select Pi SPI 0 on the GPIO pins | |||||||
| PI SPI 1 Select¹ | ■ | ■ | • | Select Pi SPI 1 on the GPIO pins | |||||||
| FPGA Flash Select | ■ | ■ | • | Select the FPGA Flash ROM (Internal Use Only) | |||||||
* The SPI port's data lines are active low (0 to select).
¹ Pi GPIO must be configured for SPI. See NR 160 (A0h)
Five devices are connected to the SPI interface. The ZX Spectrum Next must be
SPI master.
Only one of D0 through D3 can be 0 at one time. If not, the result will be no device selected
| Group Name | R | W | Data Bits | Description | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||||
| SPI Data | ■ | ■ | • | • | • | • | • | • | • | • | Read/Write data to the selected SPI device |
| Group Name | R | W | Data Bits | Description | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||||
| Prescalar MSB Value | ■ | ■ | • | • | • | Baud rate prescalar MSB | |||||
| Prescalar MSB Write Enable | ■ | ■ | • | D2:D0 write enable | |||||||
| UART Select** | ■ | ■ | 0 | ESP UART Select | |||||||
| 1 | Pi0 UART Select* | ||||||||||
* Pi GPIO must be configured for UART. See NR 160 (A0h)
** Either UART can be redirected to the joystick ports, see NR 11 (0Bh)
| Group Name | R | W | Data Bits | Description | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||||
| Read buffer status flag | ■ | • | Set if read buffer contains received bytes | ||||||||
| Transmitter busy flag | ■ | • | Set if the transmit buffer is full | ||||||||
| Read buffer full flag | ■ | • | Set if the read buffer overflowed* | ||||||||
| Read buffer near-full flag | ■ | • | Set if the read buffer in near-full (¾) | ||||||||
| Transmit buffer empty flag | ■ | • | Set if the transmit buffer is empty | ||||||||
| Receive data after error flag | ■ | • | Set if the next Rx byte was recv'd after an error** | ||||||||
| Receive framing error flag | ■ | • | Set if the Rx experienced a framing error*** | ||||||||
| Receive in break flag | ■ | • | Set if the Rx is in a break condition**** | ||||||||
| Data Transmit | ■ | • | • | • | • | • | • | • | • | Send a byte to the connected device | |
* Clears on read
** Framing or overflow
*** Clears on read; includes parity and stop bit errors
**** External device has held Tx=0 for at least 20 bit periods
Both UARTs have a 64-byte transmit buffer
| Group Name | R | W | Data Bits | Description | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||||
| Data Receive | ■ | • | • | • | • | • | • | • | • | Reads a byte from the receive buffer* | |
| Prescalar LSB Value¹ | ■ | 0 | • | • | • | • | • | • | • | Lower 7 bits of the 14-bit prescalar value LSB | |
| 1 | • | • | • | • | • | • | • | Upper 7 bits of the 14-bit prescalar value LSB | |||
* If the buffer is empty 0 is returned.
¹ The UART's baud rate is determined by the prescalar according to this formula:
Prescalar = Fsys / baudrate; Fsys = System Clock from NR 17 (11h).
Example: If the system is on a Digital display, NR 17 (11h) indicates that Fsys = 27000000.
The prescalar for a baud rate of 115200 is 27000000 / 115200 = 234
Both UARTs have a 512-byte receive buffer
| Group Name | R | W | Data Bits | Description | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||||
| Stop bits control | ■ | ■ | • | Set if 2 stop bits, clear for 1 stop bit | |||||||
| Parity type control | ■ | ■ | • | Set if odd parity, clear for even parity | |||||||
| Parity check control | ■ | ■ | • | Set to enable parity check | |||||||
| Frame size (bits) control | ■ | ■ | 0 | 0 | 5 bits | ||||||
| 0 | 1 | 6 bits | |||||||||
| 1 | 0 | 7 bits | |||||||||
| 1 | 1 | 8 bits | |||||||||
| Hardware Flow control | ■ | ■ | • | Set enables hardware flow control* | |||||||
| Transmit break control** | ■ | ■ | • | Send a byte to the connected device | |||||||
| Reset Rx and Tx Control | ■ | ■ | • | Set to immediately reset Rx, Tx and empty FIFOs | |||||||
* Honoured only on an Issue 4 ESP module, no effect on Issue 2 boards. In joystick I/O mode only CTS is available
** Asserts break on Tx when Tx becomes idle
| Group Name | R | W | Data Bits | Description | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||||
| Sprite Collision flag | ■ | • | Set if any two displayed sprites collide on screen | ||||||||
| Max. No. of Sprites per line flag | ■ | • | Set if maximum no. of sprites per line exceeded | ||||||||
| Current Pattern Index Select² | ■ | • | • | • | • | • | • | • | Sets Current Pattern Index | ||
| Current Sprite Index Select¹ | ■ | • | • | • | • | • | • | • | Sets Current Sprite (0 - 127) | ||
* Reading the port clears all flags
¹ The current sprite and pattern index are separate quantities internally
² The pattern index is 6-bit in bits D0 through D5 and selects pattern 0 - 63 in the pattern RAM. Each pattern is 256 bytes long. D7 can be used to offset 128 bytes halfway through the pattern; this accommodates 4-bit sprites whose patterns are 128 bytes in size.
| Group Name | R | W | Data Bits | Description | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||||
| Attribute Data | ■ | • | • | • | • | • | • | • | • | Attribute Data | |
Writes the current sprite's attributes. Each sprite has either 4 or 5 attributes and after all are written, the current sprite pointer is advanced to the next sprite. The pointer wraps from 127 to 0.
| Group Name | R | W | Data Bits | Description | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||||
| Pattern Data | ■ | • | • | • | • | • | • | • | • | Pattern Data | |
Writes a byte to the current pattern address and advances the current address by one. The pattern address is changed by writing the pattern index in port 12347 (303Bh). A pattern index indicates the start of a 256-byte range of data used to define an 8-bit sprite pattern or a 128-byte range of data use to define a 4-bit sprite pattern.
| Group Name | R | W | Data Bits | Description | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||||
| DMA Control | ■ | ■ | • | • | • | • | • | • | • | • | DMA command value |
The zxnDMA implements a subset of the Zilog Z80DMA architecture while adding a burst mode primarily used to play digital music. Accessing the DMA via port 11 (0Bh) rather than 107 (6Bh) selects the DMA compatibility mode (Z80DMA). See https://www.specnext.com/the-zxndma/
| Group Name | R | W | Data Bits | Description | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||||
| Memory Write Mapping Control | ■ | ■ | • | Enable Mapping for Memory Writes | |||||||
| Layer 2 Display Control | ■ | ■ | • | Enable Layer 2 Display | |||||||
| Memory Read Mapping Control | ■ | ■ | • | Enable Mapping for Memory Reads | |||||||
| Active/Shadow Control | ■ | ■ | 0 | Map Active Layer 2¹ | |||||||
| 1 | Map Shadow Layer 2² | ||||||||||
| Reserved | ■ | 0 | 0 | Reserved, Must be 0 | |||||||
| Layer 2 Map Type Select | ■ | ■ | 0 | 0 | First 16K of Layer 2 in the bottom 16K | ||||||
| 0 | 1 | Second 16K of Layer 2 in the bottom 16K | |||||||||
| 1 | 0 | Third 16K of Layer 2 in the bottom 16K | |||||||||
| 1 | 1 | First 48K of Layer 2 in the bottom 48K | |||||||||
* Memory pointed at by NR 18 (12h) or NR 19 (13 h) can be mapped into the lower 16K or 48K if Layer 2 memory mapping is enabled in D2 and/or D0. This mechanism is separate from MMU and will overlay the paging state set by MMU but only if the memory access type matches the enable condition (Read-only, Write-only)
¹ See NR 18 (12h)
² See NR 19 (13h)
The current memory mapping is maintained by the hardware in eight MMUs with each MMU, numbered MMU0 – MMU7, holding an 8K page number currently mapped into corresponding eight 8K slots of the Z80's 64K memory space. The individual MMUs can be programmed via NextREGs 80 – 87 (50h – 57h).
The traditional banking mechanism used in various Spectrum models is via ports 7FFDh, DFFDh, 1FFDh and EFF7h with writes to these ports making changes to one or more MMUs in the hardware.
The 128K Spectrum used port 7FFDh, the +3 used 7FFDh and 1FFDh and the ZX Spectrum Next extends that with port DFFDh to increase the range of 16K banks that can be paged into the top 16K.
Russian ZX Spectrum models extended the banking in various ways to support up to 1MB of memory. The ZX Spectrum Next, also supports some of these banking methods which modify the behaviour of ports 7FFDh and DFFDh. The current memory mapping mode is held in NextREG 143 (8Fh) and can be one of standard ZX Spectrum, Pentagon 512K or Pentagon 1024K. The ZX Spectrum Next normally operates in standard Spectrum mode.
In standard spectrum mode, ports 7FFDh and 1FFDh operate as on the +3 and as described above.
Port DFFDh adds four bits to extend the three bit bank number in bits D2:D0 of port 7FFDh so that the full range of the ZX Spectrum
ZX Spectrum Next User Manual, 3rd Edition (ISBN 978-1-5272-5496-1), written and illustrated by Phoebus R. Dokos. Copyright © 2020-2024 Phoebus Dokos / SpecNext Ltd. Licensed under CC BY-NC-SA 4.0. This is a transcription and can contain errors; check any doubt against the printed page.