NOTE
The following Hardware Ports are not listed:
ULA 254 (FEh), Legacy Memory Paging 3765 (7FFDh), 8189 (1FFDh), 57341 (DFFDh), 61431 (EFF7h), Layer 2 4667 (123Bh) and ULAplus 65339 (FF3Bh) / 48955 (BF3B)
Ports are arranged according to their function.
Please also consult the ports.txt document found in your System/Next™ distribution for a complete list of ports
| Group Name | R | W | Data Bits | Description | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||||
| Screen Mode Select | ■ | ■ | 0 | 0 | 0 | Std: DFILE0+COLOURFILE0 @ 4000h | |||||
| 0 | 0 | 1 | Shd: DFILE1+COLOURFILE1 @ 6000h | ||||||||
| 0 | 1 | 0 | HC: DFILE @ 4000h, COLOURFILE @ 6000h | ||||||||
| 1 | 1 | 0 | HR: even DFILE @ 4000h, odd DFILE @6000h | ||||||||
| HiRes Colour Scheme Select | ■ | ■ | 0 | 0 | 0 | BRIGHT Black on White | |||||
| 0 | 0 | 1 | BRIGHT Blue on Yellow | ||||||||
| 0 | 1 | 0 | BRIGHT Red on Cyan | ||||||||
| 0 | 1 | 1 | BRIGHT Magenta on Green | ||||||||
| 1 | 0 | 0 | BRIGHT Green on Magenta | ||||||||
| 1 | 0 | 1 | BRIGHT Cyan on Red | ||||||||
| 1 | 1 | 0 | BRIGHT Yellow on Blue | ||||||||
| 1 | 1 | 1 | BRIGHT White on Black | ||||||||
| Frame Interrrupt Control | ■ | ■ | • | 1 to Disable ULA Frame Interrupt | |||||||
| Timex MMU Select¹ | ■ | ■ | • | Timex Horizontal MMU Bank Select | |||||||
* Only readable if NR 8 (08h):D2 = 1
¹ Not implemented on the ZX Spectrum Next
| Group Name | R | W | Data Bits | Description | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||||
| Current X Position | ■ | • | • | • | • | • | • | • | • | Value 0 – 255* | |
* Returns the current X position of the mouse 0 - 255.
The value wraps from 255 to 0 on a right movement and from 0 to 255 on a left movement.
| Group Name | R | W | Data Bits | Description | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||||
| Current Y Position | ■ | • | • | • | • | • | • | • | • | Value 0 - 255* | |
* Returns the current Y position of the mouse 0 - 255.
The value decrements and wraps from 255 to 0 on a downward movement and increments and wraps from 0 to 255 on an upward movement.
| Group Name | R | W | Data Bits | Description | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||||
| Mouse Button Flags¹ | ■ | • | Left Mouse button status | ||||||||
| • | Right Mouse button status | ||||||||||
| • | Middle Mouse button status | ||||||||||
| Mouse Wheel Position² | ■ | • | • | • | • | Mouse Wheel position (Wraps) | |||||
¹ Pressed = 1, Not Pressed = 0
² Value 0 to 15. Upwards scroll 15 to 0 – wraps to 15; Downards scroll 0 to 15 – wraps to 0
| Group Name | R | W | Data Bits | Description | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||||
| Joystick Movement Status | ■ | • | Right (pin 4) | ||||||||
| • | Left (pin 3) | ||||||||||
| • | Down (pin 2) | ||||||||||
| • | Up (pin 1) | ||||||||||
| Joystick Button Status | ■ | • | Fire 1 (MD = B) (pin 6) | ||||||||
| • | Fire 2 (MD = C) (pin 9) | ||||||||||
| • | MD = A (0 on Kempston) | ||||||||||
| • | MD Start (0 on Kempston) | ||||||||||
Joystick ports can be placed in I/O mode via NR 11 (0Bh)
Kempston joysticks and Mega Drive Pads share ports but MD pads use more bits
The X/Y/Z buttons on MD pads can be read via NR 178 (B2h)
All twelve MD pad buttons can be assigned to the keyboard – See NR 05 (05h)
When using an MD pad in more limited joystick modes, the excess buttons can generate keypresses if so programmed
| Group Name | R | W | Data Bits | Description | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||||
| Joystick Movement Status | ■ | • | Right (pin 4) | ||||||||
| • | Left (pin 3) | ||||||||||
| • | Down (pin 2) | ||||||||||
| • | Up (pin 1) | ||||||||||
| Joystick Button Status | ■ | • | Fire 1 (MD = B) (pin 6) | ||||||||
| • | Fire 2 (MD = C) (pin 9) | ||||||||||
| • | MD = A (0 on Kempston) | ||||||||||
| • | MD Start (0 on Kempston) | ||||||||||
Joystick ports can be placed in I/O mode via NR 11 (0Bh)
Kempston joysticks and Mega Drive Pads share ports but MD pads use more bits
The X/Y/Z buttons on MD pads can be read via NR 178 (B2h)
All twelve MD pad buttons can be assigned to the keyboard – See NR 05 (05h)
When using an MD pad in more limited joystick modes, the excess buttons can generate keypresses if so programmed
| Group Name | R | W | Data Bits | Description | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||||
| Selected Register Status | ■ | • | • | • | • | • | • | • | • | Value in selected register of active PSG | |
| Active PSG Control | ■ | 0 | 0 | Reserved | |||||||
| 1 | 1 | PSG 0 made active* | |||||||||
| 1 | 0 | PSG 1 made active | |||||||||
| 0 | 1 | PSG 2 made active | |||||||||
| Stereo Channel Control¹ | ■ | 1 | Reserved, must be 1 | ||||||||
| 1 | Reserved, must be 1 | ||||||||||
| 1 | Reserved, must be 1 | ||||||||||
| • | Right Channel Enable | ||||||||||
| • | Left Channel Enable | ||||||||||
| 1 | Reserved, must be 1 | ||||||||||
| Register Select² | • | • | • | • | If 0000 selects a register from the Active PSG | ||||||
* Default value
¹ If NR 8 (08h):D1 = 1 and D7 through D4 are not 0000
| Group Name | R | W | Data Bits | Description | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||||
| Selected Register Status¹ | ■ | • | • | • | • | • | • | • | • | Value in selected register of active PSG | |
| Active PSG Register Data | ■ | • | • | • | • | • | • | • | • | Value to write to the register | |
¹ Readable if machine type is ZX Spectrum Next or ZX Spectrum +3 only.
| Group Name | R | W | Data Bits | Description | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||||
| Currently selected PSG register | ■ | • | • | • | • | • | Value of selected register of active PSG | ||||
| Reserved | ■ | • | Reserved | ||||||||
| Active PSG | ■ | 1 | 1 | PSG 0 is active | |||||||
| 1 | 0 | PSG 1 is active | |||||||||
| 0 | 1 | PSG 2 is active | |||||||||
| Group Name | R | W | Data Bits | Description | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||||
| DAC output | ■ | • | • | • | • | • | • | • | • | 8-bit unsigned sample value | |
All DACs originate from various ZX Spectrum peripherals and compatible models and are kept for compatibility. DACs are enabled by setting NR 8 (08h):D3 = 1
¹ Found in Pentagon and ATM
² Found in SpecDRUM™
³ Found in SoundDrive 1
⁴ Found in SoundDrive 2
⁵ Found in Profi Covox
| Group Name | R | W | Data Bits | Description | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||||
| DAC output | ■ | • | • | • | • | • | • | • | • | 8-bit unsigned sample value | |
All DACs originate from various ZX Spectrum peripherals and compatible models and are kept for compatibility. DACs are enabled by setting NR 8 (08h):D3 = 1
¹ Found in GS Govox
² Found in SoundDrive 1 and Covox
³ Found in SoundDrive 2
| Group Name | R | W | Data Bits | Description | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||||
| DAC output | ■ | • | • | • | • | • | • | • | • | 8-bit unsigned sample value | |
All DACs originate from various ZX Spectrum peripherals and compatible models and are kept for compatibility. DACs are enabled by setting NR 8 (08h):D3 = 1
¹ Found in GS Govox
² Found in SoundDrive 1 and Covox
³ Found in SoundDrive 2
| Group Name | R | W | Data Bits | Description | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||||
| DAC output | ■ | • | • | • | • | • | • | • | • | 8-bit unsigned sample value | |
All DACs originate from various ZX Spectrum peripherals and compatible models and are kept for compatibility. DACs are enabled by setting NR 8 (08h):D3 = 1
¹ Found in Pentagon, ATM and SoundDrive 2
² Found in SpecDRUM™
³ Found in SoundDrive 1 and Profi Covox
| Group Name | R | W | Data Bits | Description | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||||
| RAM bank Control | ■ | ■ | • | • | • | • | Memory Bank Select for 8K - 16K region | ||||
| MapRAM Control¹ | ■ | ■ | • | MapRAM Enable | |||||||
| ConMEM Control² | ■ | ■ | • | ConMEM Enable | |||||||
¹ Can only be set once. On the original divMMC only a power cycle can reset it. The ZX Spectrum Next implementation uses NR 9 (09h) where D3 can be set,in order to reset this bit. When set, it replaces the expected esxDOS ROM with divMMC RAM bank 3
² Can be used to manually control divMMC mapping. When set it maps in divMMC; 0K - 8K will contain the esxDOS ROM, 8K - 16K will contain the selected divMMC bank (from D0 through D3). The divMMC automatically maps itself in when instruction fetches hit specific addresses in the ROM. When this happens, the esxDOS ROM (or divMMC bank 3 if mapRAM is set) appears in 0K - 8K and the selected divMMC bank appears as RAM in 8K - 16K. DivMMC automapping is normally disabled by NextZXOS. See NR 6 (06h):D4. The divMMC has been enhanced, in order to add entry points and make them programmable.
ZX Spectrum Next User Manual, 3rd Edition (ISBN 978-1-5272-5496-1), written and illustrated by Phoebus R. Dokos. Copyright © 2020-2024 Phoebus Dokos / SpecNext Ltd. Licensed under CC BY-NC-SA 4.0. This is a transcription and can contain errors; check any doubt against the printed page.