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NextREG 176 (B0h) – Extended Keys 0*

Group NameRWData BitsDescriptionHD
76543210
RIGHT Status■ •Key pressed status flag (1 = pressed)
LEFT Status■ • Key pressed status flag (1 = pressed)
DOWN Status■ • Key pressed status flag (1 = pressed)
UP Status■ • Key pressed status flag (1 = pressed)
. Status■ • Key pressed status flag (1 = pressed)
, Status■ • Key pressed status flag (1 = pressed)
" Status■ • Key pressed status flag (1 = pressed)
; Status■• Key pressed status flag (1 = pressed)

* NextREG 104 (68h) D4 stops extended keys from making entries into the 8x5 keyboard matrix

NextREG 177 (B1h) – Extended Keys 1*

Group NameRWData BitsDescriptionHD
76543210
EXTEND Status■ •Key pressed status flag (1 = pressed)
CAPS LOCK Status■ • Key pressed status flag (1 = pressed)
GRAPH Status■ • Key pressed status flag (1 = pressed)
TRUE VIDEO Status■ • Key pressed status flag (1 = pressed)
INV VIDEO Status■ • Key pressed status flag (1 = pressed)
BREAK Status■ • Key pressed status flag (1 = pressed)
EDIT Status■ • Key pressed status flag (1 = pressed)
DELETE Status■• Key pressed status flag (1 = pressed)

* NextREG 104 (68h) D4 stops extended keys from making entries into the 8x5 keyboard matrix

NextREG 178 (B2h) – Extended MD Pad Buttons

Group NameRWData BitsDescriptionHD
76543210
Left pad MODE Status■ •Button pressed status flag (1 = pressed)
Left pad Y Status■ • Button pressed status flag (1 = pressed)
Left pad Z Status■ • Button pressed status flag (1 = pressed)
Left pad X Status■ • Button pressed status flag (1 = pressed)
Right pad MODE Status■ • Button pressed status flag (1 = pressed)
Right pad Y Status■ • Button pressed status flag (1 = pressed)
Right pad Z Status■ • Button pressed status flag (1 = pressed)
Right pad X Status■• Button pressed status flag (1 = pressed)

NextREG 184 (B8) – divMMC Entry Points 0

Group NameRWData BitsDescriptionHD
76543210
0000h Automap Control■■ •1 to enable automap (instruction fetch)1
0008h Automap Control■■ • 1 to enable automap (instruction fetch)1
0010h Automap Control■■ • 1 to enable automap (instruction fetch)
0018h Automap Control■■ • 1 to enable automap (instruction fetch)
0020h Automap Control■■ • 1 to enable automap (instruction fetch)
0028h Automap Control■■ • 1 to enable automap (instruction fetch)
0030h Automap Control■■ • 1 to enable automap (instruction fetch)
0038h Automap Control■■• 1 to enable automap (instruction fetch)1

NextREG 185 (B9h) – divMMC Entry Points Valid 0

Group NameRWData BitsDescriptionHD
76543210
Entry point at 0000h■■ •1 for always*1
Entry point at 0008h■■ • 1 for always*0
Entry point at 0010h■■ • 1 for always*0
Entry point at 0018h■■ • 1 for always*0
Entry point at 0020h■■ • 1 for always*0
Entry point at 0028h■■ • 1 for always*0
Entry point at 0030h■■ • 1 for always*0
Entry point at 0038h■■• 1 for always*0

* Otherwise when ROM3 is present

NextREG 186 (BAh) – divMMC Entry Points Timing Control 0

Group NameRWData BitsDescriptionHD
76543210
Entry point at 0000h■■ •1 for instant mapping otherwise delayed0
Entry point at 0008h■■ • 1 for instant mapping otherwise delayed0
Entry point at 0010h■■ • 1 for instant mapping otherwise delayed0
Entry point at 0018h■■ • 1 for instant mapping otherwise delayed0
Entry point at 0020h■■ • 1 for instant mapping otherwise delayed0
Entry point at 0028h■■ • 1 for instant mapping otherwise delayed0
Entry point at 0030h■■ • 1 for instant mapping otherwise delayed0
Entry point at 0038h■■• 1 for instant mapping otherwise delayed0

NextREG 187 (BBh) – divMMC Entry Points 1

Group NameRWData BitsDescriptionHD
76543210
Entry point at 0066h (delayed)■■ •1 to enable automap (instr. fetch + button)1
Entry point at 0066h (instant)■■ • 1 to enable automap (instr. fetch + button)0
Entry point at 04C6h (ROM3)¹■■ • 1 to enable automap (instr. fetch/delayed)1
Entry point at 0562h (ROM3)¹■■ • 1 to enable automap (instr. fetch/delayed)1
Entry point at 04D7h (ROM3)²■■ • 1 to enable automap (instr. fetch/delayed)0
Entry point at 056Ah (ROM3)²■■ • 1 to enable automap (instr. fetch/delayed)0
Entry points at 1FF8h:1FFFh■■ • 1 to disable automap (instr. fetch/delayed)1
Entry points at 3Dxxh (ROM3)³■■• 1 to enable automap (instr. fetch/instant)1

1 Tape traps. Original divMMC + esxDOS
2 Tape traps. NextZXOS (these offer better compatibility with tape-based software)
3 Used by TR-DOS

INTERRUPTS

NextREG 192 (C0h) – Interrupt Control

Group NameRWData BitsDescriptionHD
76543210
Maskable Interrupt Mode■■ 0Pulse0
Current Z80 Interrupt Mode■ 00 Interrupt Mode 00
01 Interrupt Mode 1
10 Interrupt Mode 2
Stackless NMI Enable¹■■ • Toggle (1=enable, 0=disable)0
Reserved■■ 0 Reserved, must be 00
IM2 vector■■••• Programmable portion of IM2 vector0
Maskable Interrupt Mode■■ 1Hardware IM2²0
Interrupt Vector Generated■■ .0000 Line interrupt (Highest Priority)
0001 UART 0 Rx
0010 UART 1 Rx
0011 CTC Channel 0
0100 CTC Channel 1
0101 CTC Channel 2
0110 CTC Channel 3
0111 CTC Channel 4
1000 CTC Channel 5
1001 CTC Channel 6
1010 CTC Channel 7
1011 ULA
1100 UART 0 Tx
1101 UART 1 Tx (lowest priority)
••• NextREG 192 (C0h) D7:D5

1 The return address pushed during an NMI acknowledge cycle will be written to NextREG instead of memory (the SP will be decremented) and the first RETN after the acknowledge will take its return address from NextREG instead of memory (the SP will be incremented)
If D3 = 0 and in other circumstances (see advanced hardware manual), RETN functions normally
2 In Hardware IM2 Mode the expansion bus is the lowest priority interrupter and if no vector is supplied externally then 255 (FFh) will be generated

NextREG 194 (C2h) – NMI Return Address LSB

Group NameRWData BitsDescriptionHD
76543210
NMI Return Address■■••••••••8-bit value (LSB)*

The return address written during an NMI acknowledge cycle is always stored in this and the next (NextREG C3h) registers

NextREG 195 (C3h) – NMI Return Address MSB

Group NameRWData BitsDescriptionHD
76543210
NMI Return Address■■••••••••8-bit value (MSB)*

The return address written during an NMI acknowledge cycle is always stored in this and the previous (NextREG C2h) registers

NextREG 196 (C4h) – Interrupt Enables 0

Group NameRWData BitsDescriptionHD
76543210
ULA■■ •1 to enable*1
Line■■ • 1 to enable*0
Reserved■■ 0 0 0 0 0 Reserved must be 00
Expasion Bus I̅N̅T̅■■• 1 to enable1

* Aliases of interrupt enable bits in NextREG 34 (22h)
If a device interrupt is disabled, it enters a polled mode

NextREG 197 (C5h) – Interrupt Enables 1

Group NameRWData BitsDescriptionHD
76543210
CTC Channel 0 ZC/TO■■ •1 to enable0
CTC Channel 1 ZC/TO■■ • 1 to enable0
CTC Channel 2 ZC/TO■■ • 1 to enable0
CTC Channel 3 ZC/TO■■ • 1 to enable0
CTC Channel 4 ZC/TO■■ • 1 to enable0
CTC Channel 5 ZC/TO■■ • 1 to enable0
CTC Channel 6 ZC/TO■■ • 1 to enable0
CTC Channel 7 ZC/TO■■• 1 to enable0

If a device interrupt is disabled, it enters a polled mode

NextREG 198 (C6h) – Interrupt Enables 2

Group NameRWData BitsDescriptionHD
76543210
UART 0 Rx available¹■■ •1 to enable0
UART 0 Rx near-full¹■■ • 1 to enable0
UART 0 Tx empty■■ • 1 to enable0
Reserved■■ 0 Reserved, must be 00
UART 1 Rx available²■■ • 1 to enable0
UART 1 Rx near-full²■■ • 1 to enable0
UART 1 Tx empty■■ • 1 to enable0
Reserved■■ 0 Reserved, must be 00

1 Shared interrupt. Rx near-full overrides Rx available
2 Shared interrupt. Rx near-full overrides Rx available
If a device interrupt is disabled, it enters a polled mode

NextREG 199 (C7h) – Reserved

Group NameRWData BitsDescriptionHD
76543210
Reserved, write 0■■ 0 0 0 0 0 0 0 0Reserved, must be 00
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ZX Spectrum Next User Manual, 3rd Edition (ISBN 978-1-5272-5496-1), written and illustrated by Phoebus R. Dokos. Copyright © 2020-2024 Phoebus Dokos / SpecNext Ltd. Licensed under CC BY-NC-SA 4.0. This is a transcription and can contain errors; check any doubt against the printed page.