Note here that the 16K Bank 5, is the bank read by the ULA to determine what to show on screen for Layer 0 (and 1). The ULA connects directly to the larger memory space ignoring mapping; the screen is always 16K Bank 5, no matter where in memory it is (or if it is switched in at all). Setting D3 of Memory Paging Control (7FFDh) will have the ULA read instead from 16K Bank 7 (otherwise known as "shadow screen"), which can be used as an alternate screen. Beware that this does not map 16K bank 7 into RAM; to alter 16K bank 7 it must be mapped by other means.

Let's now examine the bit layout of port 1FFDh used by the +3.

When D0 is 0, D1 has no effect and D2 is a "vertical" ROM switch (ie between ROM0 and ROM2 or between ROM1 and ROM3). D4 at 7FFDh on the other hand is a "horizontal" ROM switch (ie. between ROM0 and ROM1, or between ROM2 and ROM3). The following diagram illustrates the various ROM switching possibilities:

It is best to think of D4 in port 7FFDh and D2 in port 1FFDh combining to form a 2-bit number (ranging from 0 to 3) which determines which ROM occupies the memory area 0000h to 3FFFh (16K Slot 1). D4 of port 7FFDh is the least significant bit and D2 of 1FFDh is the most significant bit.

ROM switching (with D0 of 1FFDh set to 0)

Tying it all together, we can easily surmise that 128 style memory management can only alter the bank addressed at C000h (For 16K banks that would be Slot 4, or for 8K MMU-type banks Slots 7 and 8). The active 16K bank at C000h is selected by writing the 3 LSBs of the 16K bank number to the bottom 3 bits of Memory Paging Control (7FFDh), and the 4 MSBs to the bottom 4 bits of Next Memory Bank Select (DFFDh). (The reason for the division is that the original Spectrum 128, having only 128k of memory, only needed 3 bits.)

This in essence constructs a "super hardware port" of sorts, very similar to the combination used to select a ROM using bits from 1FFDh and 7FFDh

"Standard Next paging" bank selection settings

If you are using the standard interrupt handler or NextZXOS routines, then any time you write to the Memory Paging Control port (7FFDh) you should also store the value in SysVars at location 5B5Ch. Any time you write to the +3 Memory Paging Control (1FFDh) you should also store the value at 5B67h. There is no corresponding system variable for the Next-only Next Memory Bank Select (DFFDh) port.

⁶ Not applicable on the ZX Spectrum Next